fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 04:38:03 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: fix missing cache flushes when clearing HTILE levels on GFX10+

Browse source 
The driver should accumulate the cache flush bits because if it uses
CP DMA for clearing the last level, it won't flush.

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12170>
This commit is contained in:
Samuel Pitoiset 2021-08-02 16:43:15 +02:00 • committed by Marge Bot
parent ebea075feb
commit ad83c06a5f
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/amd/vulkan/radv_meta_clear.c
View file

@ -1389,10 +1389,10 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
if (htile_mask == UINT_MAX) {
/* Clear the whole HTILE buffer. */
flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
} else {
/* Only clear depth or stencil bytes in the HTILE buffer. */
flush_bits =
flush_bits |=
clear_htile_mask(cmd_buffer, image, image->bo, offset, size, value, htile_mask);
}
}