Commit graph

1487 commits

Author SHA1 Message Date
Ian Romanick
ba2fa1ceaf intel/fs: Do cmod prop again after scheduling
Pre-RA scheduling can create more opportunities for CMOD propagation.
This takes advantage of that.

It may be worth doing this again in post-RA scheduling, but there are
additional problems there.

I'm a little torn about the use of the OPT() macro.  On the one hand, it
would be confusing to see dumps from INTEL_DEBUG=optimizer that don't
match the final output.  On the other hand, since register allocation
can fail, the same pass can be run multiple times.  Each time one or
both passes might or might not make progress.  This would also lead to
incongruous, confusing output.

Ice Lake
total instructions in shared programs: 14549808 -> 14548529 (<.01%)
instructions in affected programs: 231985 -> 230706 (-0.55%)
helped: 632
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 2.02 x̃: 1
helped stats (rel) min: 0.05% max: 2.56% x̄: 0.57% x̃: 0.41%
95% mean confidence interval for instructions value: -2.25 -1.79
95% mean confidence interval for instructions %-change: -0.61% -0.54%
Instructions are helped.

total cycles in shared programs: 203770850 -> 203776599 (<.01%)
cycles in affected programs: 2495653 -> 2501402 (0.23%)
helped: 282
HURT: 197
helped stats (abs) min: 1 max: 242 x̄: 20.37 x̃: 16
helped stats (rel) min: <.01% max: 11.65% x̄: 0.91% x̃: 0.64%
HURT stats (abs)   min: 2 max: 609 x̄: 58.35 x̃: 20
HURT stats (rel)   min: <.01% max: 10.97% x̄: 1.35% x̃: 0.66%
95% mean confidence interval for cycles value: 5.27 18.73
95% mean confidence interval for cycles %-change: -0.16% 0.21%
Inconclusive result (%-change mean confidence interval includes 0).

LOST:   0
GAINED: 2

Skylake
total instructions in shared programs: 13447708 -> 13446594 (<.01%)
instructions in affected programs: 216813 -> 215699 (-0.51%)
helped: 623
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 1.79 x̃: 1
helped stats (rel) min: 0.06% max: 2.86% x̄: 0.59% x̃: 0.42%
95% mean confidence interval for instructions value: -1.99 -1.59
95% mean confidence interval for instructions %-change: -0.63% -0.55%
Instructions are helped.

total cycles in shared programs: 193759224 -> 193762726 (<.01%)
cycles in affected programs: 2540035 -> 2543537 (0.14%)
helped: 249
HURT: 190
helped stats (abs) min: 2 max: 196 x̄: 16.67 x̃: 14
helped stats (rel) min: <.01% max: 4.71% x̄: 0.66% x̃: 0.62%
HURT stats (abs)   min: 2 max: 614 x̄: 40.27 x̃: 14
HURT stats (rel)   min: 0.02% max: 5.78% x̄: 0.86% x̃: 0.37%
95% mean confidence interval for cycles value: 2.57 13.39
95% mean confidence interval for cycles %-change: -0.11% 0.11%
Inconclusive result (%-change mean confidence interval includes 0).

LOST:   0
GAINED: 1

Broadwell
total instructions in shared programs: 13418631 -> 13417393 (<.01%)
instructions in affected programs: 243192 -> 241954 (-0.51%)
helped: 694
HURT: 0
helped stats (abs) min: 1 max: 31 x̄: 1.78 x̃: 1
helped stats (rel) min: 0.06% max: 2.86% x̄: 0.59% x̃: 0.44%
95% mean confidence interval for instructions value: -1.95 -1.62
95% mean confidence interval for instructions %-change: -0.62% -0.55%
Instructions are helped.

total cycles in shared programs: 200822940 -> 200829128 (<.01%)
cycles in affected programs: 2128651 -> 2134839 (0.29%)
helped: 251
HURT: 226
helped stats (abs) min: 1 max: 200 x̄: 14.32 x̃: 12
helped stats (rel) min: <.01% max: 3.56% x̄: 0.60% x̃: 0.50%
HURT stats (abs)   min: 2 max: 611 x̄: 43.28 x̃: 18
HURT stats (rel)   min: 0.02% max: 7.03% x̄: 0.93% x̃: 0.54%
95% mean confidence interval for cycles value: 7.44 18.50
95% mean confidence interval for cycles %-change: 0.02% 0.23%
Cycles are HURT.

Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs: 11569710 -> 11568829 (<.01%)
instructions in affected programs: 147862 -> 146981 (-0.60%)
helped: 487
HURT: 0
helped stats (abs) min: 1 max: 34 x̄: 1.81 x̃: 1
helped stats (rel) min: 0.12% max: 4.75% x̄: 0.57% x̃: 0.45%
95% mean confidence interval for instructions value: -2.03 -1.59
95% mean confidence interval for instructions %-change: -0.61% -0.54%
Instructions are helped.

total cycles in shared programs: 187079425 -> 187079437 (<.01%)
cycles in affected programs: 1088494 -> 1088506 (<.01%)
helped: 234
HURT: 124
helped stats (abs) min: 2 max: 282 x̄: 22.66 x̃: 16
helped stats (rel) min: 0.03% max: 7.88% x̄: 0.93% x̃: 0.75%
HURT stats (abs)   min: 1 max: 276 x̄: 42.86 x̃: 20
HURT stats (rel)   min: 0.03% max: 6.70% x̄: 0.99% x̃: 0.53%
95% mean confidence interval for cycles value: -5.54 5.61
95% mean confidence interval for cycles %-change: -0.41% -0.11%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 7746 -> 7740 (-0.08%)
spills in affected programs: 6 -> 0
helped: 1
HURT: 0

total fills in shared programs: 6264 -> 6258 (-0.10%)
fills in affected programs: 6 -> 0
helped: 1
HURT: 0

Sandy Bridge
total instructions in shared programs: 10688576 -> 10688177 (<.01%)
instructions in affected programs: 137875 -> 137476 (-0.29%)
helped: 358
HURT: 0
helped stats (abs) min: 1 max: 9 x̄: 1.11 x̃: 1
helped stats (rel) min: 0.15% max: 1.43% x̄: 0.35% x̃: 0.28%
95% mean confidence interval for instructions value: -1.18 -1.05
95% mean confidence interval for instructions %-change: -0.37% -0.32%
Instructions are helped.

total cycles in shared programs: 153397144 -> 153393046 (<.01%)
cycles in affected programs: 1220713 -> 1216615 (-0.34%)
helped: 255
HURT: 31
helped stats (abs) min: 1 max: 304 x̄: 16.71 x̃: 16
helped stats (rel) min: <.01% max: 6.70% x̄: 0.41% x̃: 0.31%
HURT stats (abs)   min: 1 max: 41 x̄: 5.29 x̃: 3
HURT stats (rel)   min: 0.02% max: 0.65% x̄: 0.16% x̃: 0.11%
95% mean confidence interval for cycles value: -17.44 -11.22
95% mean confidence interval for cycles %-change: -0.40% -0.29%
Cycles are helped.

Iron Lake
total instructions in shared programs: 8106894 -> 8105529 (-0.02%)
instructions in affected programs: 287197 -> 285832 (-0.48%)
helped: 1099
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 1.24 x̃: 1
helped stats (rel) min: 0.16% max: 4.55% x̄: 0.67% x̃: 0.61%
95% mean confidence interval for instructions value: -1.29 -1.19
95% mean confidence interval for instructions %-change: -0.70% -0.64%
Instructions are helped.

total cycles in shared programs: 188347022 -> 188344266 (<.01%)
cycles in affected programs: 3740632 -> 3737876 (-0.07%)
helped: 758
HURT: 10
helped stats (abs) min: 2 max: 38 x̄: 3.68 x̃: 2
helped stats (rel) min: <.01% max: 1.00% x̄: 0.12% x̃: 0.08%
HURT stats (abs)   min: 2 max: 4 x̄: 3.20 x̃: 4
HURT stats (rel)   min: 0.03% max: 0.07% x̄: 0.06% x̃: 0.07%
95% mean confidence interval for cycles value: -3.82 -3.35
95% mean confidence interval for cycles %-change: -0.13% -0.11%
Cycles are helped.

GM45
total instructions in shared programs: 4985449 -> 4984768 (-0.01%)
instructions in affected programs: 145154 -> 144473 (-0.47%)
helped: 547
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 1.24 x̃: 1
helped stats (rel) min: 0.16% max: 2.86% x̄: 0.66% x̃: 0.61%
95% mean confidence interval for instructions value: -1.31 -1.18
95% mean confidence interval for instructions %-change: -0.69% -0.62%
Instructions are helped.

total cycles in shared programs: 128835062 -> 128833144 (<.01%)
cycles in affected programs: 2720650 -> 2718732 (-0.07%)
helped: 517
HURT: 1
helped stats (abs) min: 2 max: 38 x̄: 3.71 x̃: 2
helped stats (rel) min: <.01% max: 0.89% x̄: 0.11% x̃: 0.07%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.04% max: 0.04% x̄: 0.04% x̃: 0.04%
95% mean confidence interval for cycles value: -4.02 -3.39
95% mean confidence interval for cycles %-change: -0.12% -0.10%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
2020-03-09 16:46:19 -07:00
Matt Turner
e924181ea8 intel/compiler: Discount NOPs from instruction counts
Scheduler changes can cause changes in the number of instructions due to
this workaround, so just don't include NOPs in the instruction counts to
prevent shader-db noise.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:12 +00:00
Matt Turner
bb3e7b0fe3 intel/compiler: Pass shader_stats for each SIMD mode
Passing shader_stats to the fs_generator constructor means that the
SIMD8 shader stats from the visitor (such as the scheduler mode) will be
reported out for the SIMD16/SIMD32 versions as well.

As you can see, we are now passing 'shader_stats' and 'stats' to
generate_code(), which is obviously odd looking. Ian rebased and
committed an old patch of mine which added the shader_stats struct on
July 30 in commit dabb5d4bee (i965/fs: Add a shader_stats struct.) and
shortly after on August 12 Jason added the brw_compile_stats struct in
commit 134607760a (intel/compiler: Fill a compiler statistics struct).

I'd like to combine the two, but I'm not sure how. shader_stats is an
input to generate_code() while brw_compile_stats is an output and is
only used by the Vulkan driver. Leave it as is for now...

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:12 +00:00
Matt Turner
e7d0460d58 intel/compiler: Pass backend_shader * to cfg_t()
As you can see, not having a pointer to the backend_shader from within
the class makes for some weird looking code.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:12 +00:00
Matt Turner
edae75037f intel/compiler: Mark visitor parameters to scheduler const
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:12 +00:00
Matt Turner
75a33e268e intel/compiler: Mark some methods and parameters const
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:11 +00:00
Matt Turner
03ac90aae5 intel/compiler: Make instructions_to_schedule a local variable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:11 +00:00
Matt Turner
43019c6f2c intel/compiler: Remove unnecessary local variables
These are already provided in the fs_reg_alloc class.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:11 +00:00
Matt Turner
3d0821a216 intel/vec4: Make implied_mrf_writes() a vec4_instruction method
Same as commit c20dc9b836 (intel/fs: Make implied_mrf_writes() an
fs_inst method.)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:11 +00:00
Francisco Jerez
70349a2252 intel/compiler: Calculate num_instructions in O(1) during register pressure calculation
And mark the variable declaration as const.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:13 -08:00
Francisco Jerez
e5e4d016b9 intel/compiler: Move register pressure calculation into IR analysis object
This defines a new BRW_ANALYSIS object which wraps the register
pressure computation code along with its result.  For the rationale
see the previous commits converting the liveness and dominance
analysis passes to the IR analysis framework.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:10 -08:00
Francisco Jerez
f6cdf66cd6 entel/compiler: Simplify new_idom reduction in dominance tree calculation
Trivial, just use a few less tokens to do the same thing.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:07 -08:00
Francisco Jerez
c9a608c090 intel/compiler: Move dominance tree data structure into idom_tree object
It makes sense to keep the result of analysis passes independent from
the IR itself.  Instead of representing the idom tree as a pointer in
each basic block pointing to its immediate dominator, the whole
dominator tree is represented separately from the IR as an array of
pointers inside the idom_tree object.  This has the advantage that
it's no longer possible to use stale dominance results by accident
without having called require() beforehand, which makes sure that the
idom tree is recalculated if necessary.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:05 -08:00
Francisco Jerez
c2a7eababf intel/compiler: Move idom tree calculation and related logic into analysis object
This only does half of the work.  The actual representation of the
idom tree is left untouched, but the computation algorithm is moved
into a separate analysis result class wrapped in a BRW_ANALYSIS
object, along with the intersect() and dump_domtree() auxiliary
functions in order to keep things tidy.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:03 -08:00
Francisco Jerez
2878817197 intel/compiler: Drop invalidate_live_intervals()
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:01 -08:00
Francisco Jerez
acf24df201 intel/compiler/vec4: Switch liveness analysis to IR analysis framework
This involves wrapping vec4_live_variables in a BRW_ANALYSIS object
and hooking it up to invalidate_analysis() so it's properly
invalidated.  Seems like a lot of churn but it's fairly
straightforward.  The vec4_visitor invalidate_ and
calculate_live_intervals() methods are no longer necessary after this
change.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:59 -08:00
Francisco Jerez
ea44de6d8c intel/compiler/fs: Switch liveness analysis to IR analysis framework
This involves wrapping fs_live_variables in a BRW_ANALYSIS object and
hooking it up to invalidate_analysis() so it's properly invalidated.
Seems like a lot of churn but it's fairly straightforward.  The
fs_visitor invalidate_ and calculate_live_intervals() methods are no
longer necessary after this change.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:57 -08:00
Francisco Jerez
bb8cfa6837 intel/compiler/vec4: Add live interval validation pass
This could be improved somewhat with additional validation of the
calculated live in/out sets and by checking that the calculated live
intervals are minimal (which isn't strictly necessary to guarantee the
correctness of the program).  This should be good enough though to
catch accidental use of stale liveness results due to missing or
incorrect analysis invalidation.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:55 -08:00
Francisco Jerez
24535604aa intel/compiler/fs: Add live interval validation pass
This could be improved somewhat with additional validation of the
calculated live in/out sets and by checking that the calculated live
intervals are minimal (which isn't strictly necessary to guarantee the
correctness of the program).  This should be good enough though to
catch accidental use of stale liveness results due to missing or
incorrect analysis invalidation.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:53 -08:00
Francisco Jerez
a9cdc14f60 intel/compiler: Pass single backend_shader argument to the vec4_live_variables constructor
The IR analysis framework requires the analysis result to be
constructible with a single argument.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:51 -08:00
Francisco Jerez
d0433971f9 intel/compiler: Pass single backend_shader argument to the fs_live_variables constructor
This removes the dependency of fs_live_variables on fs_visitor.  The
IR analysis framework requires the analysis result to be constructible
with a single argument -- The second argument was redundant anyway.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:49 -08:00
Francisco Jerez
d7e84cbb0f intel/compiler: Restructure live intervals computation code
This makes the structure of the vec4 live intervals calculation more
similar to the FS back-end liveness analysis code.  The non-CF-aware
start/end computation is moved into the same pass that calculates the
block-local def/use sets, which saves quite a bit of code, while the
CF-aware start/end computation is moved into a separate
compute_start_end() function as is done in the FS back-end.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:46 -08:00
Francisco Jerez
48dfb30f92 intel/compiler: Move all live interval analysis results into vec4_live_variables
This moves the following methods that are currently defined in
vec4_visitor (even though they are side products of the liveness
analysis computation) and are already implemented in
brw_vec4_live_variables.cpp:

> int var_range_start(unsigned v, unsigned n) const;
> int var_range_end(unsigned v, unsigned n) const;
> bool virtual_grf_interferes(int a, int b) const;
> int *virtual_grf_start;
> int *virtual_grf_end;

It makes sense for them to be part of the vec4_live_variables object,
because they have the same lifetime as other liveness analysis results
and because this will allow some extra validation to happen wherever
they are accessed in order to make sure that we only ever use
up-to-date liveness analysis results.

The naming of the virtual_grf_start/end arrays was rather misleading,
they were indexed by variable rather than by vgrf, this renames them
start/end to match the FS liveness analysis pass.  The churn in the
definition of var_range_start/end is just in order to avoid a
collision between the start/end arrays and local variables declared
with the same name.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:44 -08:00
Francisco Jerez
ba73e606f6 intel/compiler: Move all live interval analysis results into fs_live_variables
This moves the following methods that are currently defined in
fs_visitor (even though they are side products of the liveness
analysis computation) and are already implemented in
brw_fs_live_variables.cpp:

> bool virtual_grf_interferes(int a, int b) const;
> int *virtual_grf_start;
> int *virtual_grf_end;

It makes sense for them to be part of the fs_live_variables object,
because they have the same lifetime as other liveness analysis results
and because this will allow some extra validation to happen wherever
they are accessed in order to make sure that we only ever use
up-to-date liveness analysis results.

This shortens the virtual_grf prefix in order to compensate for the
slightly increased lexical overhead from the live_intervals pointer
dereference.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:43 -08:00
Francisco Jerez
3ceb496cdf intel/compiler: Mark virtual_grf_interferes and vars_interfere as const
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:41 -08:00
Francisco Jerez
ab6d792986 intel/compiler: Pass detailed dependency classes to invalidate_analysis()
Have fun reading through the whole back-end optimizer to verify
whether I've missed any dependency flags -- Or alternatively, just
trust that any mistake here will trigger an assertion failure during
analysis pass validation if it ever poses a problem for the
consistency of any of the analysis passes managed by the framework.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:39 -08:00
Francisco Jerez
65080dc8df intel/compiler: Define more detailed analysis dependency classes
I've deliberately separated this from the general analysis pass
infrastructure in order to discuss it independently.  The dependency
classes defined here refer to state changes of several objects of the
program IR, and are fully orthogonal and expected to change less often
than the set of analysis passes present in the compiler back-end.

The objective is to avoid unnecessary coupling between optimization
and analysis passes in the back-end.  By doing things in this way the
set of flags to be passed to invalidate_analysis() can be determined
from knowledge of a single optimization pass and a small set of well
specified dependency classes alone -- IOW there is no need to audit
all analysis passes to find out which ones might be affected by
certain kind of program transformation performed by an optimization
pass, as well as the converse, there is no need to audit all
optimization passes when writing a new analysis pass to find out which
ones can potentially invalidate the result of the analysis.

The set of dependency classes defined here is rather conservative and
mainly based on the requirements of the few analysis passes already
part of the back-end.  I've also used them without difficulty with a
few additional analysis passes I've written but haven't yet sent for
review.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:37 -08:00
Francisco Jerez
d966a6b4c4 intel/compiler: Introduce backend_shader method to propagate IR changes to analysis passes
The invalidate_analysis() method knows what analysis passes there are
in the back-end and calls their invalidate() method to report changes
in the IR.  For the moment it just calls invalidate_live_intervals()
(which will eventually be fully replaced by this function) if anything
changed.

This makes all optimization passes invalidate DEPENDENCY_EVERYTHING,
which is clearly far from ideal -- The dependency classes passed to
invalidate_analysis() will be refined in a future commit.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:32 -08:00
Francisco Jerez
03eb46f4a7 intel/compiler: Introduce simple IR analysis pass framework
Motivated in detail in the source code.  The only piece missing here
from the analysis pass infrastructure is some sort of mechanism to
broadcast changes in the IR to all existing analysis passes, which
will be addressed by a future commit.  The analysis_dependency_class
enum might seem a bit silly at this point, more interesting dependency
categories will be defined later on.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:30 -08:00
Francisco Jerez
27ae3c1f68 intel/compiler: Reverse inclusion dependency between brw_vec4_live_variables.h and brw_vec4.h
brw_vec4.h (in particular vec4_visitor) is logically a user of the
live variables analysis pass, not the other way around.
brw_vec4_live_variables.h requires the definition of some VEC4 IR data
structures to compile, but those can be obtained directly from
brw_ir_vec4.h without including brw_vec4.h.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:28 -08:00
Francisco Jerez
a6fc88e91b intel/compiler: Reverse inclusion dependency between brw_fs_live_variables.h and brw_fs.h
brw_fs.h (in particular fs_visitor) is logically a user of the live
variables analysis pass, not the other way around.
brw_fs_live_variables.h requires the definition of some FS IR data
structures to compile, but those can be obtained directly from
brw_ir_fs.h without including brw_fs.h.  The dependency of
fs_live_variables on fs_visitor is rather accidental and will be
removed in a future commit, a forward declaration is enough for the
moment.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:26 -08:00
Francisco Jerez
06c5c49646 intel/compiler: Nest definition of live variables block_data structures
When this commit was originally written, these two structures had the
exact same name. Subsequently in commit 12a8f2616a (intel/compiler:
Fix C++ one definition rule violations) they were renamed.

Original commit message:

> These two structures have exactly the same name which prevents the two
> files from being included at the same time and could cause serious
> trouble in the future if it ever leads to a (silent) violation of the
> C++ one definition rule.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:23 -08:00
Francisco Jerez
310aef6b59 intel/compiler: Reverse inclusion dependency between brw_cfg.h and brw_shader.h
This reflects the natural dependency relationship between brw_cfg.h
and brw_shader.h.  brw_cfg.h only requires the base IR definitions
which are now part of a separate header.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:19 -08:00
Francisco Jerez
d46fb2126d intel/compiler: Move base IR definitions into a separate header file
This pulls out the i965 IR definitions into a separate file and leaves
the top-level backend_shader structure and back-end compiler entry
points in brw_shader.h.  The purpose is to keep things tidy and
prevent a nasty circular dependency between brw_cfg.h and
brw_shader.h.  The logical dependency between these data structures
looks like:

 backend_shader (brw_shader.h) -> cfg_t (brw_cfg.h)
    -> bblock_t (brw_cfg.h) -> backend_instruction (brw_shader.h)

This circular header dependency is currently resolved by using forward
declarations of cfg_t/bblock_t in brw_shader.h and having brw_cfg.h
include brw_shader.h, which seems backwards and won't work at all when
the forward declarations of cfg_t/bblock_t are no longer sufficient in
a future commit.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:11 -08:00
Jordan Justen
cf12faef61
intel/compiler: Restrict cs_threads to 64
Our current GPGPU_WALKER code only supports up to 64 threads.

On HSW we could use up to 70 and TGL up to 112, but only if the walker
is adjusted so the width does not exceed 64. Work to support this is
in progress.

Previous to this change, we might try to downgrade to SIMD8 if the
SIMD16 shader spilled. Since HSW and TGL have the max number of
threads above 64, we would then try to emit an invalid GPGPU walker
command.

Fixes: 932045061b ("i965/cs: Emit compute shader code and upload programs")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2020-02-28 14:45:43 -08:00
Caio Marcelo de Oliveira Filho
956e4b2d37 nir, intel: Move use_scoped_memory_barrier to nir_options
This option will be used later by GLSL, so move to a common struct.

Because nir_options is filled in the compiler instead of the Vulkan
driver, fix that up.  GLSL will ignore that for now.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
2020-02-24 19:12:11 +00:00
Eric Anholt
3e16434acd nir: Move intel's intrinsic_image_coordinate_components() to core nir.
This is a query that both Intel and freedreno need to do.  We can simplify
it a lot with the new glsl_get_sampler_dim_coordinate_components()

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Ian Romanick
273b8cd1ca intel/fs: Correctly handle multiply of fsign with a source modifier
The other source of the multiply will be interpreted as a uint32_t in an
XOR instruction.  Any source modifiers with either not be interpreted at
all or will be misinterpreted due to the differing types.

If the other operand of the multiplication has a source modifier, just
emit an extra move to resolve the source modifiers.

The negation source modifier problem is difficult to reproduce due to an
algebraic optimization that changes (-a*b) to -(a*b).  However, changes
in MR !1359 push the negations back down.

On Gen7+ it might be possible to do slightly better for an abs() source
modifier by using BFI2 as a glorified copysign().

On Gen8+ it might be possible to do slightly better for a neg() source
modifier by emitting (~a ^ b).

There were no shader-db changes on any Intel platform, so I think we can
deal with that problem when it arises.

See also piglit!224.

Fixes: 06d2c11641 ("intel/fs: Add a scale factor to emit_fsign")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3780>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3780>
2020-02-19 23:51:42 +00:00
Danylo Piliaiev
d5931f285b intel/compiler: Do not qsort zero sized array
../src/intel/compiler/brw_nir_analyze_ubo_ranges.c:316:4: runtime error: null pointer passed as argument 1, which is declared to never be null
    #0 0x7f78f5916611 in brw_nir_analyze_ubo_ranges ../src/intel/compiler/brw_nir_analyze_ubo_ranges.c:316
    #1 0x7f78f255c189 in brw_codegen_wm_prog ../src/mesa/drivers/dri/i965/brw_wm.c:97
    #2 0x7f78f2565571 in brw_fs_precompile ../src/mesa/drivers/dri/i965/brw_wm.c:608
    #3 0x7f78f24edd2c in brw_shader_precompile ../src/mesa/drivers/dri/i965/brw_link.cpp:56
    #4 0x7f78f24f3af8 in brw_link_shader ../src/mesa/drivers/dri/i965/brw_link.cpp:381
    #5 0x7f78f39a302a in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3119
    #6 0x7f78f3a43826 in create_new_program ../src/mesa/main/ff_fragment_shader.cpp:1133
    #7 0x7f78f3a43d00 in _mesa_get_fixed_func_fragment_program ../src/mesa/main/ff_fragment_shader.cpp:1163
    #8 0x7f78f325ddcd in update_program ../src/mesa/main/state.c:134
    #9 0x7f78f325fe64 in _mesa_update_state_locked ../src/mesa/main/state.c:360
    #10 0x7f78f32600f1 in _mesa_update_state ../src/mesa/main/state.c:394
    #11 0x7f78f2b3e587 in clear ../src/mesa/main/clear.c:169
    #12 0x7f78f2b3e587 in _mesa_Clear ../src/mesa/main/clear.c:242

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Danylo Piliaiev
d596795d4d brw_fs: Avoid zero size vla
../src/intel/compiler/brw_fs.cpp:2247:46: runtime error: variable length array bound evaluates to non-positive value 0
    #0 0x7f78f5697678 in fs_visitor::assign_constant_locations() ../src/intel/compiler/brw_fs.cpp:2247
    #1 0x7f78f571d29e in fs_visitor::optimize() ../src/intel/compiler/brw_fs.cpp:7361
    #2 0x7f78f574eb84 in fs_visitor::run_fs(bool, bool) ../src/intel/compiler/brw_fs.cpp:8022
    #3 0x7f78f575641b in brw_compile_fs ../src/intel/compiler/brw_fs.cpp:8408
    #4 0x7f78f255c8e4 in brw_codegen_wm_prog ../src/mesa/drivers/dri/i965/brw_wm.c:123
    #5 0x7f78f2565571 in brw_fs_precompile ../src/mesa/drivers/dri/i965/brw_wm.c:608
    #6 0x7f78f24edd2c in brw_shader_precompile ../src/mesa/drivers/dri/i965/brw_link.cpp:56
    #7 0x7f78f24f3af8 in brw_link_shader ../src/mesa/drivers/dri/i965/brw_link.cpp:381
    #8 0x7f78f39a302a in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3119
    #9 0x7f78f3a43826 in create_new_program ../src/mesa/main/ff_fragment_shader.cpp:1133
    #10 0x7f78f3a43d00 in _mesa_get_fixed_func_fragment_program ../src/mesa/main/ff_fragment_shader.cpp:1163
    #11 0x7f78f325ddcd in update_program ../src/mesa/main/state.c:134
    #12 0x7f78f325fe64 in _mesa_update_state_locked ../src/mesa/main/state.c:360
    #13 0x7f78f32600f1 in _mesa_update_state ../src/mesa/main/state.c:394
    #14 0x7f78f2b3e587 in clear ../src/mesa/main/clear.c:169
    #15 0x7f78f2b3e587 in _mesa_Clear ../src/mesa/main/clear.c:242

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Danylo Piliaiev
d4e395a27d brw_nir: Cast bitshift to unsigned
../src/intel/compiler/brw_nir.c:979:40: runtime error: left shift of 1 by 31 places cannot be represented in type 'int'
    #0 0x7f78f590d10b in brw_nir_apply_sampler_key ../src/intel/compiler/brw_nir.c:979
    #1 0x7f78f590e07b in brw_nir_apply_key ../src/intel/compiler/brw_nir.c:1057
    #2 0x7f78f5754b45 in brw_compile_fs ../src/intel/compiler/brw_fs.cpp:8347
    #3 0x7f78f255c8e4 in brw_codegen_wm_prog ../src/mesa/drivers/dri/i965/brw_wm.c:123
    #4 0x7f78f2565571 in brw_fs_precompile ../src/mesa/drivers/dri/i965/brw_wm.c:608
    #5 0x7f78f24edd2c in brw_shader_precompile ../src/mesa/drivers/dri/i965/brw_link.cpp:56
    #6 0x7f78f24f3af8 in brw_link_shader ../src/mesa/drivers/dri/i965/brw_link.cpp:381
    #7 0x7f78f39a302a in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3119
    #8 0x7f78f3a43826 in create_new_program ../src/mesa/main/ff_fragment_shader.cpp:1133
    #9 0x7f78f3a43d00 in _mesa_get_fixed_func_fragment_program ../src/mesa/main/ff_fragment_shader.cpp:1163
    #10 0x7f78f325ddcd in update_program ../src/mesa/main/state.c:134
    #11 0x7f78f325fe64 in _mesa_update_state_locked ../src/mesa/main/state.c:360
    #12 0x7f78f32600f1 in _mesa_update_state ../src/mesa/main/state.c:394
    #13 0x7f78f2b3e587 in clear ../src/mesa/main/clear.c:169
    #14 0x7f78f2b3e587 in _mesa_Clear ../src/mesa/main/clear.c:242

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Caio Marcelo de Oliveira Filho
79788b8f7f intel/gen12: Take into account opcode when decoding SWSB
The interpretation of the fields is different depending whether the
instruction is a SEND/MATH or not.

This fixes the disassembly output for non-SEND/MATH instructions that
have both in-order and out-of-order dependencies.  Their dependencies
were wrongly represented as `@A $B` when the correct would be `@A
$B.dst`.

Fixes: 6154cdf924 ("intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.")
Fixes: 83612c0127 ("intel/disasm/gen12: Disassemble software scoreboard information.")
Acked-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
2020-02-18 09:17:51 -08:00
Francisco Jerez
8d3b86e34a intel/fs/gen7+: Implement discard/demote for SIMD32 programs.
At this point this simply involves fixing the initialization of the
sample mask flag register to take the right dispatch mask from the
thread payload, and fixing sample_mask_reg() to return f1.1 for the
second half of a SIMD32 thread.  This improves Manhattan 3.1
performance by 2.4%±0.31% (N>40) on my ICL with SIMD32 enabled
relative to falling back to SIMD16 for the shaders that use discard.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:49 -08:00
Francisco Jerez
04c7d3d4b1 intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.
In SIMD32 programs that don't use discard, the upper 16 bits of the UD
result of sample_mask_reg() don't contain the sample mask of the upper
16 channels as one would expect.  Stop pretending we are returning a
valid 32-bit mask.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:49 -08:00
Francisco Jerez
1c6853a9be intel/fs: Refactor predication on sample mask into helper function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
a792e11f5c intel/fs/gen7+: Swap sample mask flag register and FIND_LIVE_CHANNEL temporary.
FIND_LIVE_CHANNEL was using f1.0-f1.1 as temporary flag register on
Gen7, instead use f0.0-f0.1.  In order to avoid collision with the
discard sample mask, move the latter to f1.0-f1.1.  This makes room
for keeping track of the sample mask of the second half of SIMD32
programs that use discard.

Note that some MOVs of the sample mask into f1.0 become redundant now
in lower_surface_logical_send() and lower_a64_logical_send().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>x
2020-02-14 14:31:48 -08:00
Francisco Jerez
083fd96a97 intel/fs: Use helper for discard sample mask flag subregister number.
Use it instead of hard-coding f0.1 for the sample mask of programs
that use discard.  This will make the task easier when we replace f0.1
with another flag register location in order to support discard with
SIMD32 shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
a6bc11a789 intel/fs: Make sample_mask_reg() local to brw_fs.cpp and use it in more places.
It's only really useful there.  This will avoid confusion with another
helper with a similar purpose I'm about to introduce that will be
useful in multiple files from the FS back-end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
b84fa0b31e intel/fs/gen11: Work around dual-source blending hangs in combination with SIMD32.
The SIMD8 dual-source blending framebuffer write messages seem to have
trouble releasing the pixel scoreboard dependency in SIMD32 dispatch
mode, which leads to hangs.  I have a better workaround for this which
doesn't involve disabling SIMD32 when dual-source blending is enabled,
but I'm still investigating some issues with it.  Limit the dispatch
width to SIMD16 in such cases for the moment in order to make the CI
happy on ICL with SIMD32 fragment shaders enabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
57dee58c82 intel/fs: Set src0 alpha present bit in header when provided in message payload.
Currently the "Source0 Alpha Present to RenderTarget" bit of the RT
write message header is derived from brw_wm_prog_data::replicate_alpha.
However the src0_alpha payload is provided anytime it's specified to
the logical message.  This could theoretically lead to an
inconsistency if somebody provided a src0_alpha value while
brw_wm_prog_data::replicate_alpha was false, as I'm planning to do in
a future commit in order to implement a hardware workaround.

Instead calculate the header bit based on whether a src0_alpha value
was provided to the logical message, which guarantees the same
behavior on pre-ICL and ICL+ (the latter used an extended descriptor
bit for this which didn't suffer from the same issue).  Remove the
brw_wm_prog_data::replicate_alpha flag.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00