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intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.

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In SIMD32 programs that don't use discard, the upper 16 bits of the UD
result of sample_mask_reg() don't contain the sample mask of the upper
16 channels as one would expect.  Stop pretending we are returning a
valid 32-bit mask.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2020-01-04 16:11:23 -08:00
parent 1c6853a9be
commit 04c7d3d4b1
1 changed files with 2 additions and 3 deletions
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5
src/intel/compiler/brw_fs.cpp
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@ -4290,7 +4290,7 @@ sample_mask_reg(const fs_builder &bld)
} else {
assert(v->devinfo->gen >= 6 && bld.dispatch_width() <= 16);
return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7),
BRW_REGISTER_TYPE_UD);
BRW_REGISTER_TYPE_UW);
}
}
@ -5337,8 +5337,7 @@ emit_predicate_on_sample_mask(const fs_builder &bld, fs_inst *inst)
subreg + inst->group / 16).subnr);
} else {
bld.group(1, 0).exec_all()
.MOV(brw_flag_subreg(subreg + inst->group / 16),
retype(sample_mask, BRW_REGISTER_TYPE_UW));
.MOV(brw_flag_subreg(subreg + inst->group / 16), sample_mask);
}
if (inst->predicate) {