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Author SHA1 Message Date
Erik Faye-Lund
a6da9d7147 amd: use imm-helpers 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
 2023-06-29 07:08:19 +00:00
Joshua Ashton
68b9ad0ba7 radv: Do not enable robustness for push constants with robustBufferAccess2 
There is no spec text requiring this behaviour, it is only for buffers.

Signed-off-by: Joshua Ashton <joshua@froggi.es>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23885>
 2023-06-28 20:49:30 +00:00
Konstantin Seurer
1e2f647fbb radv/rt: Hash stages using radv_hash_shaders 
The hash also depends on the radv_pipeline_key as well as the flags. The
pipeline layout will also play a role when we implement inline
descriptor sets and push constants.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23747>
 2023-06-28 19:45:25 +00:00
Konstantin Seurer
de1092e256 radv/rt: Fix caching non-recursive stages 
The hash used for insertion is calculated in a different way than the
hash used for lookup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23747>
 2023-06-28 19:45:25 +00:00
Samuel Pitoiset
3f7ea95bc9 radv: inline more values in radv_emit_fb_ds_state() 
These are no longer adjusted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23887>
 2023-06-28 13:21:44 +00:00
Samuel Pitoiset
5010ab8fff radv: stop emitting TILE_SURFACE_ENABLE for the ZRANGE_PRECISION workaround 
The only case that matters is when the fb is emitted, but HTILE is
already disabled there using DB_RENDER_CONTROL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23887>
 2023-06-28 13:21:44 +00:00
Samuel Pitoiset
7b8c6cedcf radv: allow NV_device_generated_commands with RADV_DEBUG=noibs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Samuel Pitoiset
277b2afd70 radv/amdgpu: add support for executing DGC cmdbuf with RADV_DEBUG=noibs 
This contains some preliminary work to be able to execute DGC cmdbuf
on the compute queue because IB2 doesn't exist.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Samuel Pitoiset
82c60b41e9 radv/amdgpu: add more small helpers for managing CS 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Rhys Perry
79d935ceaf radv: use nir_opt_intrinsics 
No fossil-db changes (navi21).

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
 2023-06-27 18:53:50 +00:00
Alyssa Rosenzweig
069cca9d66 treewide: Remove unused builders 
-Wunused-variables kicks in now that it can see through the init.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
 2023-06-27 18:13:02 +00:00
Alyssa Rosenzweig
173b9ee69a treewide: Use nir_builder_create more 
perl -p0e 's/nir_builder_init\(&([^,]*), /\1 = nir_builder_create(/g' -i $(git grep -l nir_builder_init)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
 2023-06-27 18:13:02 +00:00
Alyssa Rosenzweig
815efcdf7e nir: Use nir_builder_create 
perl -p0e 's/nir_builder ([^;]*);\s*nir_builder_init\(&\1, /nir_builder \1 = nir_builder_create(/g' -i $(git grep -l nir_builder_init)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
 2023-06-27 18:13:02 +00:00
Konstantin Seurer
17f3f5fa85 amd: Use nir_ instead of nir_build_ helpers 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
 2023-06-27 17:37:54 +00:00
Samuel Pitoiset
9b00867327 radv/amdgpu: workaround a kernel bug when replacing sparse mappings 
AMDGPU has a bug when clearing mappings for BOs that are always valid
in VM with OP_REPLACE.

See https://lists.freedesktop.org/archives/amd-gfx/2023-June/094648.html

The current workaround is to re-use OP_MAP/OP_UNMAP until all stable
kernels have the fix.

This partially reverts "radv/winsys: update sparse mappings with
OP_REPLACE instead of OP_MAP/OP_UNMAP".

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23741>
 2023-06-27 13:13:03 +00:00
Samuel Pitoiset
51caece74c radv/amdgpu: skip adding per VM BOs for sparse during CS BO list build 
This should be similar but it will help for re-introducing
OP_MAP/ON_UNMAP instead of OP_REPLACE.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23741>
 2023-06-27 13:13:03 +00:00
Konstantin Seurer
b0beca8c7a vulkan/rmv,radv: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer
e0641ed59f radv/rgp: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer
3e11640127 radv/rra: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer
15d6618a12 radv: Add radv_trace_mode 
...and add the RADV specific trace modes to the VK instance.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer
7a7b1a4f71 radv: Call radv_pipeline_init_scratch per shader 
Compute pipelines only have one shader, which was not handled correctly
in the case of ray tracing pipelines. Adding radv_shader as an argument
allows us to handle the ray tracing prolog. The original loop is inlined
into its only user (radv_pipeline_graphics.c).

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23812>
 2023-06-27 06:04:18 +00:00
Vitaliy Triang3l Kuzmin
f9e6d35f65 radv: Enable VK_EXT_fragment_shader_interlock 
ACO only currently - not available in LLVM.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
ec0778f59e radv: Disable VRS forcing with Primitive Ordered Pixel Shading 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
787a553262 radv: Apply the POPS missed overlap hardware bug workaround 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
3831860b20 radv: Handle Primitive Ordered Pixel Shading in DB_SHADER_CONTROL 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
37e325fe15 radv: Enable the null export workaround with POPS 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
7eabc5d6fc radv: Enable POPS collision wave ID shader argument 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
50e680d05a radv: Declare POPS collision wave ID shader argument 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
1812819e66 radv: Ensure 1x1 shading rate on GFX10.3 with interlock execution mode 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
08c582ea69 radv: Detect the use of Primitive Ordered Pixel Shading 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
5449a2c988 radv: Remove unconditional POPS_DRAIN_PS_ON_OVERLAP setting 
This hardware hang workaround (PAL waMiscPopsMissedOverlap) is needed only
on some Vega chips, and only for 8 or more samples per pixel. It has a
significant performance cost (around 1.5x-2x in
nvpro-samples/vk_order_independent_transparency), so it should be precisely
configured when setting up Primitive Ordered Pixel Shading.

It was added in 47b780be21, when POPS was not
used in Mesa, with the change being described as "this may not be needed
yet, but let's set it now".

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Samuel Pitoiset
82e2802b7d radv/amdgpu: add a helper to get a new IB 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>
 2023-06-26 09:10:10 +00:00
Samuel Pitoiset
148f42be1d radv/amdgpu: rename old_ib_buffers to ib_buffers 
No need to prefix with 'old' actually because this is just an array
of IB buffers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>
 2023-06-26 09:10:10 +00:00
Samuel Pitoiset
d74de65069 radv/amdgpu: use cs_finalize() when growing a CS 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>
 2023-06-26 09:10:10 +00:00
Samuel Pitoiset
437456b47c radv/amdgpu: use the array of IB buffers for the chained IB path 
For executing IB on the compute queue (ie. IB2 isn't supported), we
will need to break chaining, this is a first step towards this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>
 2023-06-26 09:10:10 +00:00
Samuel Pitoiset
81e308df72 radv/amdgpu: do not set the IB size when ending a CS with RADV_DEBUG=noibs 
This was only necessary for preambles/postambles, let's clarify this
by determining the IB info from the first IB in the array instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>
 2023-06-26 09:10:10 +00:00
Samuel Pitoiset
df0c742543 radv/amdgpu: rework growing a CS with the chained IB path slightly 
This should allow us to use cs_finalize().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>
 2023-06-26 09:10:09 +00:00
Samuel Pitoiset
c11a62a7b0 radv/amdgpu: use the correct IB size when growing a CS with RADV_DEBUG=noibs 
The current IB size is copied when radv_amdgpu_cs_add_old_ib_buffer()
is called, which might not be the real IB size because we might still
pad the CS with NOP packets after.

Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>
 2023-06-26 09:10:09 +00:00
Samuel Pitoiset
0f8864e047 radv: adjust alignment of the preprocess buffer with DGC 
The preprocess buffer is the buffer used to generate the cmdbuf. It
was aligned to 256 bytes but the correct alignment is actually
ac_gpu_info::ib_alignment.

Otherwise, if a DGC IB is executed like a IB1, this hits an assertion
in radv_amdgpu_cs_submit() because the alignment is incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23764>
 2023-06-23 17:17:08 +00:00
Samuel Pitoiset
06cdf222a6 radv: only dirty the active push constant stages with DGC 
It's unnecessary to dirty all stages.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23761>
 2023-06-23 16:56:44 +00:00
Samuel Pitoiset
3b329e195e radv: only dirty the index type when necessary with DGC 
This should only be needed for non-indexed draws and it's already
dirty if the DGC binds an index buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23761>
 2023-06-23 16:56:44 +00:00
Samuel Pitoiset
2d97cc89fb radv/amdgpu: dump all cs with RADV_DEBUG=noibs 
It was only dumping the oldest.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23646>
 2023-06-23 16:35:22 +00:00
Samuel Pitoiset
8af705a856 radv/amdgpu: fix dumping cs with RADV_DEBUG=noibs 
The ib_buffer is NULL now.

Fixes: 50e6b16855 ("radv/amdgpu: Use fallback submit for queues that can't use IBs.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23646>
 2023-06-23 16:35:21 +00:00
Samuel Pitoiset
ae7721d163 radv: reserve more space in CS for SQTT 
Otherwise, it can hit an assertion.

Fixes: 7893040f80 ("radv: Add stricter space checks.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23826>
 2023-06-23 13:51:13 +00:00
Timur Kristóf
3b21c59fc3 aco: Remove unneeded stage related info fields. 
Cleanup of various fields with redundant information.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>
 2023-06-23 12:49:05 +00:00
Timur Kristóf
6028c146d5 radv: Set aco_shader_info::hw_stage 
ACO will rely on this field instead of guessing
the stage internally.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>
 2023-06-23 12:49:05 +00:00
Tatsuyuki Ishi
b69a1b4153 vulkan: Migrate shader module hash to BLAKE3. 
Shaders are the largest thing we hash now, so they benefit from a faster
hash.

Change the field name from `sha1` to `hash` to avoid tying the definition
to a particular algorithm. This doubles down as a precaution against
callers still assuming a 20-byte hash (in which case the compilation will
error out).

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22571>
 2023-06-23 09:28:04 +00:00
Mike Blumenkrantz
e15a4e6e1a radv: pre-init surface info 
this is costly to do at render time, so avoid it when possible

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23770>
 2023-06-22 13:36:13 +00:00
Mike Blumenkrantz
df6749ed56 radv: inline radv_can_enable_dual_src() 
this is unexpectedly heavy

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23601>
 2023-06-21 18:59:07 +00:00
Mike Blumenkrantz
8b73109a93 radv: remove redundant intermediate variable in radv_is_mrt0_dual_src() 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23601>
 2023-06-21 18:59:07 +00:00