These are the package versions currently shipped by Fedora. This allows
using system packages by setting
export MESON_PACKAGE_CACHE_DIR=/usr/share/cargo/registry/
Of course, other distros may place it somewhere else.
Ubuntu matches versions on syn and unicode-ident but is a tiny bit off
on quote and proc-macro2. However, given how far I was able to bump the
versions with only a tiny meson tweak to syn, I think it should work
with the Ubuntu versions as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26726>
They're enough of a special case that things are going to get confusing
when we start adding bit sizes to fmul/ffma. Let's make them a special
case so they can assert all their things.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
The main change here is that we match on src2 first and then src1. This
lets make some of the src2 code common because src2 never moves around
if it's a register. This change also has another subtle effect: None
sources now work everywhere.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
We need to be able to tell the difference between `F64` and other GPR
source types. In order for this to work, we also have to tighten up
some of the requirements round GPR and SSA sources.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
For propagating OpDAdd, we need to check for negative zero because
negative zero is the no-op, not add with zero. We were also propagating
the upper and lower halves of fp64 sources wrong. While we're here, use
`let ... else` instead of an `if let` pattern a couple places.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26743>
This removes the last unknown flag from read/write instructions.
Because we now handle the write in CP_SET_DRAW_STATE more correctly when
emulating, we also have to update the control register definitions and
draw state emulation code to adjust.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
It seems like starting with a6xx, the SQE has a special register space
for reading/writing the state of the processor itself, mainly used for
saving/restoring its state in preemption. Add support for disassembling
it, removing one of the unknown flags bits.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
Turns out a5xx already had store, although not load. It was using the
high bit of the unknown flags for this.
Note that a6xx does use the high bit, and we fall back to not decoding
it at all here before properly decoding it in the next commit. Splitting
up the commits seems worth this small breakage.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26691>
When creating the swapchain, this queue is created, but it was never
freed in wsi_wl_swapchain_free along with the rest of the resources.
Signed-off-by: Dudemanguy <random342@airmail.cc>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26052>
The depth clear value is provided from 3DSTATE_WM_HZ_OP now.
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
The xe2 xml will be updated in following commits. Commit message
has been updated by Jianxun.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
ir3_nir_lower_preamble cannot handle 64b @load/store_preamble so we have
to make sure ir3_nir_opt_preamble will never produce them. Up to now,
nir_lower_locals_to_regs was run after preamble lowering so 64b locals
could still be around when lowering the preamble. This patch moves
running this pass, as well as ir3_nir_lower_64b_regs, to before the
preamble lowering.
Fixed Piglit tests:
- spec@arb_gpu_shader_fp64@execution@fs-indirect-temp-double-dst
- spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-frexp-dvec4-variable-index
This patch has no impact on shader-db.
Note: a few cleanup passes used to be run after nir_lower_locals_to_regs
(nir_opt_algebraic, nir_opt_constant_folding) and after
ir3_nir_lower_64b_regs (nir_lower_alu_to_scalar, nir_copy_prop). As far
as I can tell, these are not necessary anymore when running the register
lowering earlier so this patch removes them.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26737>
@decl_reg intrinsics must be in the first block so it's convenient to be
able to create an insertion point after all @decl_regs when the first
block needs to be split.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26737>
Doing it at bind-time causes a 1.4% overhead (among all driver calls) in
Overwatch 2. !24502 mentions that it can be precomputed in case overhead
is a concern, so do it here.
max_waves is stored directly in the radv_shader struct, because
ac_shader_config conforms to LLVM ABI and we cannot add anything custom,
and radv_shader_info needs to be determined from NIR only.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26692>
