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iris,isl: Adjust driver for several commands of clear color (xe2)

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The xe2 xml will be updated in following commits. Commit message
has been updated by Jianxun.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
This commit is contained in:
Rohan Garg 2022-07-06 14:02:00 +02:00 • committed by Marge Bot
parent 2d273c520c
commit 9512f61cd8
2 changed files with 18 additions and 2 deletions
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8
src/gallium/drivers/iris/iris_state.c
View file

@ -1454,10 +1454,16 @@ struct iris_vertex_buffer_state {
struct iris_depth_buffer_state {
/* Depth/HiZ/Stencil related hardware packets. */
#if GFX_VER < 20
uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
GENX(3DSTATE_STENCIL_BUFFER_length) +
GENX(3DSTATE_HIER_DEPTH_BUFFER_length) +
GENX(3DSTATE_CLEAR_PARAMS_length)];
#else
uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
GENX(3DSTATE_STENCIL_BUFFER_length) +
GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
#endif
};
#if INTEL_NEEDS_WA_1808121037
@ -7627,6 +7633,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
}
if (zres && ice->state.hiz_usage != ISL_AUX_USAGE_NONE) {
#if GFX_VER < 20
uint32_t *clear_params =
cso_z->packets + ARRAY_SIZE(cso_z->packets) -
GENX(3DSTATE_CLEAR_PARAMS_length);
@ -7635,6 +7642,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
clear.DepthClearValueValid = true;
clear.DepthClearValue = zres->aux.clear_color.f32[0];
}
#endif
}
iris_batch_emit(batch, cso_z->packets, sizeof(cso_z->packets));

12
src/intel/isl/isl_emit_depth_stencil.c
View file

@ -171,7 +171,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
#if GFX_VERx10 >= 125
db.TiledMode = isl_encode_tiling[info->depth_surf->tiling];
db.MipTailStartLOD = info->depth_surf->miptail_start_level;
#if GFX_VERx10 < 20
db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage);
#endif
db.RenderCompressionFormat =
isl_get_render_compression_format(info->depth_surf->format);
#elif GFX_VER >= 9
@ -194,7 +196,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
#endif
#if GFX_VER >= 12
#if GFX_VER == 12
db.ControlSurfaceEnable = db.DepthBufferCompressionEnable =
isl_aux_usage_has_ccs(info->hiz_usage);
#endif
@ -282,9 +284,11 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
.MOCS = info->mocs,
};
#if GFX_VER < 20
struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
GENX(3DSTATE_CLEAR_PARAMS_header),
};
#endif
assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
isl_aux_usage_has_hiz(info->hiz_usage));
@ -384,6 +388,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
isl_surf_get_array_pitch_sa_rows(info->hiz_surf) >> 2;
#endif
#if GFX_VER < 20
clear.DepthClearValueValid = true;
#if GFX_VER >= 8
clear.DepthClearValue = info->depth_clear_value;
@ -404,6 +409,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
default:
unreachable("Invalid depth type");
}
#endif
#endif
}
#endif /* GFX_VER >= 6 */
@ -420,7 +426,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
#if GFX_VER < 20
GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
dw += GENX(3DSTATE_CLEAR_PARAMS_length);
#endif
#endif /* GFX_VER < 20 */
#endif /* GFX_VER >= 6 */
}