Commit graph

184774 commits

Author SHA1 Message Date
Nanley Chery
5f93f97892 iris: Use common res fields for imported planes
Instead of putting the aux plane info in the aux fields, just use the
same iris_resource fields for all planes.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768>
2023-12-26 18:40:38 +00:00
Nanley Chery
a0f3c0a246 iris: Inline import_aux_info
This function is only used once. By inlining it, we can more easily
compare the CCS plane import code with the clear color plane import
code.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768>
2023-12-26 18:40:38 +00:00
Nanley Chery
81d132d5ea iris: Use helpers for generic aux plane importing
Inline iris_resource_finish_aux_import and reimplement it with the
helper functions for managing resource planes. Provides more testing for
the helper functions and simplifies the code.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768>
2023-12-26 18:40:38 +00:00
Nanley Chery
733607cc37 iris: Simplify a plane count check in from_handle
Instead of checking the plane count in order to finish importing the aux
info, just check the plane index. Planes are added in reverse, so we'll
have the complete number of planes once we reach plane zero.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768>
2023-12-26 18:40:38 +00:00
Nanley Chery
79222e5884 iris: Simplify get_main_plane_for_plane
Dropping the mod_info parameter simplifies a future commit.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768>
2023-12-26 18:40:38 +00:00
Chia-I Wu
d9ba75e2e1 Revert "vk/util: ignore unsupported feature structs"
This reverts commit eb5bb5c784.  The
commit broke drivers which do not initialize
vk_physical_device::properties.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26813>
2023-12-25 20:36:34 +00:00
Karol Herbst
bc9fe6637b ci: merge debian-rusticl-testing into debian-testing
There is really no point anymore having it split out.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26807>
2023-12-25 16:18:41 +00:00
Yonggang Luo
6d4577799c ci/microsoft: Update the image-tag and image-path for msvc2019/msvc2022
Update the image-path from x64 to x86_64 for consistence with other platform

This is also cause the python to be updated to python3.12

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
cb50d0cabf ci/msvc: Split the install of rust and d3d out of mesa_deps_test.ps1
There is no need repeatedly downloading rust and d3d when building the docker locally

Download glext.h from github

Remove src directory and .git directory once compiling finished

Split piglit and depq compiling out

Clean middle files of piglit and depq
ci/msvc: Improve fetch source of spirv_samples_source

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
6e8c3a585a ci/msvc: Stick VK-GL-CTS to specific version 56114106d860c121cd6ff0c3b926ddc50c4c11fd
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
85bbc1a753 ci/msvc: Stick deqp-runner to version v0.16.1
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
5109790cf9 ci/msvc: Install both msvc2019 and msvc2022
Currently only msvc2019 are used

This is did intentionally, so we have a history script install msvc2019 only within vs2022

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
14e624bf43 ci/msvc: Install msvc2019 only from vs2022
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
24c40cafc4 ci/msvc: Upgrade to vs2022 build tools
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
25a560b622 ci/msvc: Remove &windows_msvc_image_tag
This is hard to understand and complicated

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
c0ad42fe34 ci/msvc: Improve msvc init
Now when choose different version of msvc, there is no need rebuild windows-msvc docker

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
a2595dbf3b ci/msvc: Rename vs to msvc for consistence
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
4d6d0a24ed ci/msvc: Rename vs2019 to msvc
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
543e872d90 ci/msvc: Split install vulkan sdk out of choco
packaging are installed because python 3.12 need it

Install of vulkan-sdk improved so that it's can be running in non-docker environment

Now vulkan-sdk have separate script so that it can be updated without update MSVC

THe choco installed packages is almost freeze to update, so split install of vulkan sdk
out of it for avoid update it when update VULKAN_SDK_VERSION on local computer

--params="/InstallDir:C:\python3" won't take effect, drop it for not misleading

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
9e89e7a7c2 ci/msvc: Install graphics tools(DirectX debug layer) easy to stuck, place it at the beginning
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Yonggang Luo
09ca7b3d9e ci/msvc: update flex and bison to winflexbison3
winflexbison3 is from github and faster, other than that, bison in winflexbison is too old(year 2007)

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736>
2023-12-24 11:46:43 +00:00
Eric Engestrom
7e8db6aedf meson: always define {,DRAW_}LLVM_AVAILABLE one way or the other
With the usual benefits of `#if` instead of `#ifdef` (mostly the fact
that typos can be build failures instead of silently being interpreted
as if 0).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3863>
2023-12-24 10:01:39 +00:00
Eric Engestrom
ac5a27917d ci: fix farm restore pipelines
A few lines above, we disable pipelines for farm disables, but we were
missing a condition to run the container & build jobs when re-enabling
a farm, leading to invalid pipelines where test jobs for that farm are
created but the container & build jobs are missing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26809>
2023-12-24 09:30:52 +00:00
Eric Engestrom
d75643f400 ci: disable collabora farm as it is currently offline
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26810>
2023-12-24 09:27:15 +00:00
Juan A. Suarez Romero
c05261a7d8 ci/v3dv: add new failures
These failures started with eb5bb5c784 ("vk/util: ignore unsupported
feature structs").

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26808>
2023-12-24 00:48:10 +01:00
Samuel Pitoiset
551924aa87 ci: apply two bugfixes for VKCTS
These are needed for RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26798>
2023-12-22 20:12:39 +00:00
Rohan Garg
3e46ee61d5 intel/fs/xe2+: Lift CPS dispatch width restrictions on Xe2+.
These restrictions don't seem to be applicable anymore, and limiting
to SIMD8 wouldn't work since we're no longer building shaders with
that dispatch width.

[ Francisco: This one-liner change was squashed by Rohan Garg into a
  previous version of my patch "Stop building SIMD8 programs", but it
  makes more sense as a separate commit -- Formatted as a separate
  patch. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605>
2023-12-22 10:37:00 -08:00
Ian Romanick
84b53e1a54 intel/fs/xe2+: Pass correct dispatch_width to fs_generator for geometry-processing stages.
Instead of hard-coding a dispatch_width value which is no longer
correct on Xe2+.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605>
2023-12-22 10:37:00 -08:00
Francisco Jerez
3f92dde55e intel/fs/xe2+: Stop building SIMD8 shaders for geometry stages (VS/TCS/TES/GS).
They are no longer suppored by the fixed-function hardware.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605>
2023-12-22 10:37:00 -08:00
Francisco Jerez
6877916155 intel/fs/xe2+: Stop building SIMD8 fragment shaders.
They are no longer suppored by the fixed-function hardware.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605>
2023-12-22 10:37:00 -08:00
Francisco Jerez
7397ba61c2 intel/fs/xe2+: Stop building SIMD8 compute-like shaders (CS/BS/TS/MS).
SIMD8 kernels are no longer able to utilize the ALUs efficiently,
since they have twice the vector width as previous platforms.  However
even though there aren't many reasons to use it, SIMD8 is still
supported by the instruction set technically, and it will still be
used for some SIMD-lowering sequences.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605>
2023-12-22 10:37:00 -08:00
Francisco Jerez
69cc72e50a anv/gfx12: Hook up dual-SIMD8 fragment shader dispatch.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
4ec54e84da iris/gfx12: Hook up dual-SIMD8 fragment shader dispatch.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
ccb5795938 intel/gfx12: Enable SIMD8 dispatch in 3DSTATE_PS for FS multipolygon dispatch.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
4868408e6e intel/genxml: Add 3DSTATE_PS definitions needed for dual-SIMD8 dispatch on Gfx12+.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
1f2c44dc21 intel/compiler: Attempt to build dual-SIMD8 variant of fragment shaders on gfx12+ platforms.
Similar to other FS dispatch modes, attempt to build a dual-SIMD8
program if the regular SIMD8 program didn't spill and doubling the
amount of space for varyings doesn't cause us to go over the thread
payload limit.  Dual-SIMD8 builds in combination with coarse pixel
shading are currently not handled.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
261d07f398 intel: Add debug flag for enabling dual-SIMD8 fragment shader dispatch.
Note that this option isn't enabled by default yet pending additional
performance evaluation.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
28aec45eed intel/fs/gfx12: Implement multi-polygon format of render target array index in PS payload.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
5b1ab77423 intel/fs/gfx12: Implement multi-polygon format of back/front-facing flag in PS payload.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
4672fcbc76 intel/fs: Fix PS thread payload setup for depth_w_coef_reg.
It's not replicated per SIMD16 half of a SIMD32 thread on the PS
payload.  Make fs_visitor::payload::depth_w_coef_reg a scalar rather
than an array.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
09ea840987 intel/fs: No need to copy null destinations in lower_simd_width.
The copy would be discarded immediately.  Until now we were relying on
DCE to eliminate these, but it seems like in some cases MOVs into the
null register emitted by lower_simd_width() are never eliminated,
likely because a lower_simd_width() call has been introduced close to
the bottom of optimize() which isn't follow by any additional DCE
passes.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
5e0760a993 intel/fs/gfx12: Don't consider multipolygon PS to have packed dispatch.
This fixes a number of regressions and hangs in multipolygon fragment
shaders that have FIND_LIVE_CHANNEL sequences which would otherwise
lead to access of a dead channel.  Note that the failures don't seem
to be reproducible in simulation.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
8f92baa5d3 intel/fs/gfx12+: Don't set nir_divergence_single_prim_per_subgroup option for fragment shaders.
Flat-shaded inputs and other per-primitive values can no longer be
considered to be uniform across fragment shader subgroups due to
multipolygon dispatch.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
6bf99e6a45 intel/compiler: Don't change types for copies from ATTR file.
Since the <8;8,0> regions they use in multipolygon mode could violate
regioning restrictions in some cases, depending on the execution type
of the instruction.  Note that the assertion is removed from
try_copy_propagate() since a more accurate check is used within that
function than what fs_inst::can_change_types() can do.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
2ed36050fb intel/fs: Don't copy-propagate ATTR registers in multi-polygon FS shaders when invalid.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Jordan Justen
3f89fa63e6 intel/compiler: Pass max_polygons to copy-prop from fs_visitor.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
b62ad4e028 intel/fs: Rework layout of FS vertex setup data in ATTR file to support multi-polygon dispatch.
The updated layout includes one copy of each plane parameter per
channel of the SIMD thread, in order to allow channels to process
different polygons.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
a844c0b185 intel/fs: Fix fs_reg::component_size() to handle two-dimensional register regions.
Add code to calculate the size in bytes of arbitrary two-dimensional
regions for FIXED_GRF and ARF registers.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:31 +00:00
Francisco Jerez
83a0252e8d intel/fs: Pass builder to per_primitive_reg().
Matches prototype of interp_reg(), will be useful in a subsequent commit.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:30 +00:00
Francisco Jerez
8e9f09dbe5 intel/fs: Provide component index explicitly to interp_reg().
Main motivation is that for multipolygon PS shaders the i-th plane
parameter for the j-th input attribute will no longer necessarily be a
scalar, since different channels may be processing different polygons
with different input plane parameters, so simply taking a component()
of the result of interp_reg() will no longer work.  Instead of
duplicating the multipolygon handling logic in every caller of
interp_reg(), fold the component() call into interp_reg() so we can
replace it with multipolygon-correct code more easily.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
2023-12-22 18:05:30 +00:00