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intel/fs/xe2+: Lift CPS dispatch width restrictions on Xe2+.

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These restrictions don't seem to be applicable anymore, and limiting
to SIMD8 wouldn't work since we're no longer building shaders with
that dispatch width.

[ Francisco: This one-liner change was squashed by Rohan Garg into a
  previous version of my patch "Stop building SIMD8 programs", but it
  makes more sense as a separate commit -- Formatted as a separate
  patch. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605>
This commit is contained in:
Rohan Garg 2023-12-01 20:17:54 -08:00 • committed by Caio Oliveira
parent 84b53e1a54
commit 3e46ee61d5
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw_fs.cpp
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@ -7643,7 +7643,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
"using SIMD8 when dual src blending.\n");
}
if (key->coarse_pixel) {
if (key->coarse_pixel && devinfo->ver < 20) {
if (prog_data->dual_src_blend) {
v8->limit_dispatch_width(8, "SIMD16 coarse pixel shading cannot"
" use SIMD8 messages.\n");