Commit graph

7983 commits

Author SHA1 Message Date
Samuel Pitoiset
a3b3a7d36a radv: remove unused code for compiling PS epilogs as part of pipelines
Since we switched to the "on-demand" path for GPL, this is dead code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
2023-12-06 08:01:46 +00:00
Samuel Pitoiset
725fc0ec03 radv: switch to on-demand PS epilogs for GPL
RADV currently has two paths for PS epilogs:
- the first one is mostly used by GPL to compile fragment shader epilogs
  as part of the graphics pipeline. It's supposed to be optimal because
  fragment shader epilogs are compiled in the pipeline and eventually
  cached.
- the second one (the "on-demand" path) is required when some dynamic
  states are used because otherwise it's just impossible to compile the
  fragment shader. These epilogs are compiled during cmdbuf recording
  when all needed info are known, they are also cached in memory. This
  is the main path for Zink.

Having two different paths isn't ideal for maintenance but there is
another problem. On RDNA3, alpha to coverage needs to be exported as
part of MRTZ when either depth/stencil/samplemask are exported. The
problem being that with GPL, the PSO multisample state can be NULL when
the frag shader lib is created, which means that we can't know if atc
needs to be exported or not, even if it's static. The solution seems to
to always use on-demand fragment shader epilogs for GPL on RDNA3.

So far, I think that switching to on-demand PS epilogs unconditionally
for GPL shouldn't hurt performance and that will simplify a lot of
things.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
2023-12-06 08:01:45 +00:00
Samuel Pitoiset
3678482f1e radv: set combinedImageSamplerDescriptorCount to 1 for multi-planar formats
RADV compacts all descriptors for multi-planar images into one
combined image sampler, so it should be 96, and not eg. 192 for a two
planes format.

Fixes new CTS
dEQP-VK.binding_model.descriptor_buffer.ycbcr_sampler.*array.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26498>
2023-12-05 22:27:19 +00:00
Samuel Pitoiset
13dcbdcdf3 radv: make sure to reset the stipple line state when it's disabled
In a scenario like:
CmdBindPipeline(stipple line enabled)
CmdDraw()
CmdBindPipeline(stipple line disabled)
CmdDraw()

The second draw wasn't resetting the stipple line state and this might
have caused issues, though it's uncovered by VK CTS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26429>
2023-12-05 18:29:30 +00:00
Samuel Pitoiset
e88973fd02 radv: change the reset stipple pattern mode for adjacent lines
Ported from RadeonSI. This isn't covered by VK CTS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26429>
2023-12-05 18:29:29 +00:00
Samuel Pitoiset
16d5ffc3ee radv: update the reset stipple pattern mode
PAL recently changed the mode. This doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26429>
2023-12-05 18:29:29 +00:00
Samuel Pitoiset
949fdc9a73 radv: advertise VK_EXT_depth_clamp_zero_one
RADV already implements this behavior, so enabling this extension is
a no-op.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26443>
2023-12-05 18:10:31 +00:00
Samuel Pitoiset
338319741c radv: add DGC support for mesh shader only
This only implements mesh shaders with DGC because task shaders are
really tricky. I will address them later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
2023-12-05 14:17:39 +00:00
Samuel Pitoiset
eb3e1bdfe6 radv: only initialize the VTX base SGPR if non-zero with DGC
Otherwise, its value is incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
2023-12-05 14:17:39 +00:00
Samuel Pitoiset
1deedc70db radv: only initialize the VBO reg if VBOs are bound with DGC
With mesh shader there is no VBO at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
2023-12-05 14:17:39 +00:00
Samuel Pitoiset
400cfa0eba radv: remove never used binds_state for DGC
This has been removed a while ago.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
2023-12-05 14:17:39 +00:00
Yonggang Luo
83a5fb9faf util: Fixes note: the alignment of ‘_Atomic long long int’ fields changed in GCC 11.
This is a improve of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22121

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23961>
2023-12-05 09:26:08 +00:00
Friedrich Vock
d6d68ceda1 radv: Enable compute dispatch tunneling
Compute tunneling can considerably lower the latency of high-priority
compute work. Enabling it is beneficial in cases where high-priority
work is dispatched while the GPU is already busy with other work (e.g.
rendering on GFX). This is the case in VR compositors that dispatch
latency-sensitive compositing work to ACE while GFX is busy rendering
the next frame.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26462>
2023-12-04 12:32:47 +00:00
Eric Engestrom
778000ec7f radv: update symbols that have become aliases for newer ones
All of these have been renamed in the spec (usually by being promoted);
renamed them in our code too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26490>
2023-12-04 10:45:48 +00:00
Felix bridault
059391b631 radv: use 32bit va range for sparse descriptor buffers
Fixes: 5c5735fd68 ("radv: advertise VK_EXT_descriptor_buffer")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26482>
2023-12-04 09:59:29 +00:00
Samuel Pitoiset
9027c6d8ca radv: adjust assertions for multi-layer resolves with the HW/FS paths
Only compute supports layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
70556739e0 radv: only re-initialize DCC for one level for the HW resolve path
The source image can only have one level, so only level in the
destination image needs to be re-initialized.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
91aaf0c663 radv: remove unused layers support for the HW/FS resolve paths
The driver always fallbacks to the compute resolve path when either
the source or destination images have layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
aae2595390 radv: stop performing redundant resolves with the HW resolve path
This path was quadratic...
Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
e425f92f3e radv: simplify creating image views for src resolve images
The Vulkan spec says:

"If samples is not VK_SAMPLE_COUNT_1_BIT, then imageType must be
 VK_IMAGE_TYPE_2D, flags must not contain
 VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT, mipLevels must be equal to 1..."

So, the source image is always 2D with no mipmaps.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
bd54592487 radv: remove radv_pipeline_key::dynamic_color_write_mask
When this state is dynamic, the common runtime code sets the write mask
to 0xf which prevents color exports to be removed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26400>
2023-12-01 15:50:04 +00:00
Martin Roukala (né Peres)
a6f22aa182 radv: disable meshShaderQueries on gfx10.3
They have been causing hangs intermitently in CI for the past week,
until it finally caught my attention and forced me spend a couple of
hours bisecting the issue.

We'll re-introduce support for it when the issue is fixed.

Fixes: b975d4e800 ("radv: enable meshShaderQueries on GFX10.3")
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26450>
2023-12-01 15:17:48 +00:00
Samuel Pitoiset
ced313eec8 radv: make sure to prefetch the compute shader for DGC
It was never prefetched. These two helpers should be refactored with
radv_dispatch() though.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
2023-12-01 12:25:46 +00:00
Samuel Pitoiset
ab6cf1592f radv: fix bogus interaction between DGC and RT with descriptor bindings
pipeline_is_dirty was never TRUE because it's emitted in the before
helper. This might fix bad interactions between DGC and RT because
they both use compute shaders and descriptor bindings need to be
re-emitted.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
2023-12-01 12:25:46 +00:00
Tatsuyuki Ishi
eb0419a1aa radv: Remove aspect mask "expansion" for copy_image.
The Vulkan spec says multi-planar images can only be copied on a
per-plane basis. The COLOR_BIT to "all planes" expansion applies to
image memory barriers which is completely unrelated.

Remove the expansion logic to simplify the code. Add assertions to
clearly describe the invariant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26364>
2023-12-01 01:52:04 +00:00
Lynne
aff59c63eb radv: change queue family order in radv_get_physical_device_queue_family_properties
Fixes: 748b7f80ef ("radv: Move sparse binding into a dedicated queue.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26428>
2023-11-30 22:45:49 +00:00
Bas Nieuwenhuizen
748b7f80ef radv: Move sparse binding into a dedicated queue.
1) This better reflects the reality that we only have one timeline
   of sparse binding changes.

2) Allows making it a threaded queue from the start in prep of
   explicit sync stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
2023-11-29 17:37:37 +00:00
Bas Nieuwenhuizen
00faefa08e radv: Remove the sparse binding queue from coherent images.
Never access the image on the queue family, so no need.

(Technically not sure if this is needed for Vulkan, somewhat of
 a backstop in case apps do it)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
2023-11-29 17:37:37 +00:00
Bas Nieuwenhuizen
6ff98f9313 radv: Add implementation of cmd buffers for a sparse binding queue.
None of the commands are allowed on these ...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
2023-11-29 17:37:37 +00:00
Alyssa Rosenzweig
d50d9eccad ac,radv,radeonsi: use common 1D texture lowering
It was pulled from ac.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26397>
2023-11-29 14:04:15 +00:00
Konstantin Seurer
11897376c7 radv/rt: Skip null checks for small case counts
The individual cases make sure the sbt_idx is not null implicitly
because the handles are always != 0.

Totals from 60 (22.56% of 266) affected shaders:
Instrs: 47841 -> 47655 (-0.39%)
CodeSize: 255028 -> 253460 (-0.61%)
Latency: 1179658 -> 1225311 (+3.87%); split: -0.02%, +3.89%
InvThroughput: 224122 -> 232851 (+3.89%); split: -0.02%, +3.92%
Copies: 12049 -> 12043 (-0.05%); split: -0.37%, +0.32%
Branches: 3312 -> 3290 (-0.66%)
PreSGPRs: 3494 -> 3472 (-0.63%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25089>
2023-11-28 22:58:35 +00:00
Konstantin Seurer
fe674f67b1 radv/rt: Use a helper for inlining non-recursive stages
So we don't have to write the same logic multiple times.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25089>
2023-11-28 22:58:35 +00:00
Samuel Pitoiset
02ef01fa95 radv: enable DGC preprocessing for IBO
This seems to improve performance for Starfield by +1% and Halo Infinite
by +15%!

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10025
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
2023-11-28 14:07:37 +00:00
Samuel Pitoiset
e59a16bbb8 radv: use an indirect draw when IBO isn't updated as part of DGC
To remove the dependency on the cmd buffer state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
2023-11-28 14:07:37 +00:00
Samuel Pitoiset
2807e27231 radv: set the stream VA for DGC graphics
This will be used to emit indirect draws when needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
2023-11-28 14:07:37 +00:00
Samuel Pitoiset
88bbdfd23e radv: remove useless NIR instructions when emitting IBO with DGC
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172>
2023-11-28 14:07:37 +00:00
Marek Olšák
e0a24c7fe0 ac/nir: add kill_layer flag to VS/GS/NGG lowering
When the framebuffer state has only 1 layer, the output has no effect.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26274>
2023-11-24 15:37:24 +00:00
Samuel Pitoiset
ad7efdea6e radv: do not set OREO_MODE to fix rare corruption on GFX11
Ported from RadeonSI 3f108e7615.
Seems to be a recommendation from the AMD hw team.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26333>
2023-11-23 17:22:04 +00:00
Samuel Pitoiset
46cc7ffb79 radv: add missing FDCC_CONTROL bits for GFX1103 R2
Ported from RadeonSI.
Found by inspection, untested.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26318>
2023-11-23 13:56:53 +00:00
Samuel Pitoiset
ab34603115 radv: disable TC-compatible HTILE on Tonga and Iceland
According to RadeonSI, TC-compat HTILE have issues on Tonga/Iceland
(first GFX8 chips) and a bunch of games seem to have issues.

Let's disable it instead of using a feature that is known broken.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7101
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3894
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26204>
2023-11-23 12:55:47 +00:00
Samuel Pitoiset
b975d4e800 radv: enable meshShaderQueries on GFX10.3
GFX11 support will come later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:49 +00:00
Samuel Pitoiset
6c7265338d radv: add support for task shader invocations queries on GFX10.3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:49 +00:00
Samuel Pitoiset
623b7033c5 radv: make some gang functions non-static
They will be used to create a gang CS when beginning a query if not
already present.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:49 +00:00
Samuel Pitoiset
1b3efecd56 radv: rework gfx10_copy_gds_query() slightly
To prepare for the same function with ACE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:49 +00:00
Samuel Pitoiset
b7d668a819 radv: add support for mesh shader invocations queries on GFX10.3
Also emulated with a GDS atomic counter in shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:49 +00:00
Samuel Pitoiset
48aabaf225 radv: do not harcode the pipeline stats mask for query resolves
Otherwise, mesh/task shader invocations would be ignored.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:49 +00:00
Samuel Pitoiset
272ad65397 radv: bump the pipeline state query size to 14 on GFX10.3
GFX10.3 doesn't natively support mesh/task shader invocations query
and they need to be emulated in shaders. In order to share more code
between GFX10.3 and GFX11, it's easier to use the same size as GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:49 +00:00
Samuel Pitoiset
7b13500a99 radv: define new pipeline statistics indices for mesh/task on GFX11
GFX11 uses pipeline statistics for mesh/task queries but on GFX10.3
they need to be emulated. Though the number of mesh/task shader
invocations would be copied to the pipeline statistics range to
simplify the implementation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:49 +00:00
Samuel Pitoiset
2b93e9a02b radv: add support for mesh primitives queries on GFX10.3
This query is emulated using a GDS atomic counter in shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:48 +00:00
Samuel Pitoiset
bc6d29b0ca radv: add radv_physical_device::emulate_mesh_shader_queries for GFX10.3
GFX11 supports them natively but not GFX10.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
2023-11-21 15:24:48 +00:00