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Author SHA1 Message Date
Brian Paul
a2eb8bdcc7 st/mesa: get rid of unneeded ureg_writemask() 2010-07-23 13:50:09 -06:00
Brian Paul
e393350904 st/mesa: fix bug in emit_adjusted_wpos() 
If we bias x,y we still need to pass through z,w in case the shader
reads gl_FragCoord.z or .w.

Fixes fd.o bug 29183 (piglit glsl-bug-22603).

NOTE: This is a candidate for the 7.8 branch.
 2010-07-23 13:42:06 -06:00
Eric Anholt
c65f4fd5ae i965: Cleanly fail programs with unsupported array access. 
This should be more useful for developers and for bug triaging than
just generating wrong code.
 2010-07-23 10:54:08 -07:00
Eric Anholt
35bbbf4742 i965: Add support for VS relative addressing of temporary arrays. 
Fixes glsl-vs-arrays.  Bug #27388.
 2010-07-23 10:46:42 -07:00
Brian Paul
41e7347a17 draw: add small ybias factor for drawing wide points 
Fixes minor rasterization error detected by some tests.
 2010-07-23 10:32:58 -06:00
Brian Paul
6c3b9fa5fd docs: document new extensions for Gallium 2010-07-23 10:32:58 -06:00
Michal Krol
8122baf8ba softpipe: Check for NULL pointer in sp_destroy_tile_cache(). 2010-07-23 16:20:37 +02:00
Michal Krol
a0fc83b277 softpipe: Check for NULL pointer in sp_destroy_tex_tile_cache(). 2010-07-23 16:20:36 +02:00
Christoph Bumiller
0811b09669 nv50: implement depth clamp 2010-07-23 15:53:15 +02:00
Thomas Hellstrom
a96feddddb xorg/vmwgfx: Implement early mode pruning based on max fb size. 
Also move some initialization from screen init to pre-init, now
that it is possible.

Also import a new vmwgfx drm (1.3) header.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
 2010-07-23 04:48:33 +02:00
Thomas Hellstrom
cec7d6a4de st/xorg: Init the Gallium3D / libkms resources in pre-init. 
This makes it possible to prune modes already in pre-init.
We also keep these resources alive across server generations, and
they are implicitly closed on server exit.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
 2010-07-23 04:48:32 +02:00
Thomas Hellstrom
f3ddffc392 st/xorg: Kill a couple of compilation warnings 
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
 2010-07-23 04:48:32 +02:00
Thomas Hellstrom
6ffa23b8fe st/xorg vmwgfx/xorg: Add a pre-init customizer callback 
Add a customizer callback just before initial config setting, so that the
customizer code can initialize the mode validator using the drm
file-descriptor.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
 2010-07-23 04:48:32 +02:00
Thomas Hellstrom
a7a126bdfa st/xorg: Add a possibility to prune modes and limit fb allocation size based on max fb size. 
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
 2010-07-23 04:48:32 +02:00
Jakob Bornecrantz
2299ff4c6b llvmpipe: Partially fix resource texture from_handle 2010-07-22 20:26:35 -07:00
Jakob Bornecrantz
dc544d87a2 llvmpipe: Don't align values already aligned 2010-07-22 20:26:35 -07:00
Jakob Bornecrantz
095e99ddf6 i915g: Rename winsys debug options 2010-07-22 20:26:35 -07:00
Jakob Bornecrantz
5ccab575fd i915g: Allow wrapping with software pipes 2010-07-22 20:26:35 -07:00
Jakob Bornecrantz
37dabfeef7 i915g: Set total_nblocksy in from_handle 2010-07-22 20:26:35 -07:00
Jakob Bornecrantz
5de2678b4e i915g: Add some debug prints in texture code 2010-07-22 20:26:35 -07:00
Jakob Bornecrantz
4eaa671052 i915g: Ifdef out debug code on non-debug builds 2010-07-22 20:26:35 -07:00
Jakob Bornecrantz
e36a082214 tgsi: Fix error message on invalid swizzle parse 2010-07-22 20:26:35 -07:00
Kristian Høgsberg
eeaab2047c glx: Drop screen argument to GetGLXDRIDrawable 
We'll just get it from the returned drawable when we need it.
 2010-07-22 22:36:37 -04:00
Kristian Høgsberg
7b7845a076 glx: Move WaitGL, WaitX, UseXFont to context vtable functions 2010-07-22 22:24:00 -04:00
Kristian Høgsberg
31819830b6 glx: Allocate the __GLXcontext in the DRI drivers 2010-07-22 22:16:32 -04:00
Kristian Høgsberg
ab434f6b76 glx: Use _Xglobal_lock for protecting extension display list 
Avoids double locking glXLock in the X wire to event handlers.
 2010-07-22 21:11:20 -04:00
Brian Paul
c20a3628c7 glsl: remove invalid _mesa_problem() call 
Fixes fd.o bug 29206.
 2010-07-22 16:35:46 -06:00
Brian Paul
815e79e72c draw: re-order optimization passes depending on LLVM version, 32/64-bit 
This is a work-around for an apparent bug in LLVM seen with piglit's
glsl-vs-sqrt-zero test.
 2010-07-22 16:09:03 -06:00
Brian Paul
ca3238f3fc draw: added new assertions to clipping code 2010-07-22 11:18:54 -06:00
Eric Anholt
63ba1ec3c1 i965: Respect VS/VP point size result when enabled. 
Fixes glsl-vs-point-size.
 2010-07-22 10:06:55 -07:00
Eric Anholt
4ea71cbd0e i965: Fix the disasm output for da16 src widths. 
This has confused me twice now.  It's a fixed width of 4 (usually a
region description of <4,4,1>), not 1.  If it was 1, we'd have been
skipping all over register space.
 2010-07-22 10:06:55 -07:00
Eric Anholt
86fb92f59c i965: Avoid extra MOV in VS indirect register reads. 2010-07-22 10:06:55 -07:00
Eric Anholt
b69ef5744a i965: Fix up VS temporary array access for fixed index offset != 0. 2010-07-22 10:06:55 -07:00
Henri Verbeet
2fdff50999 r600: Flip point sprite coordinates when rendering to an FBO. 
This supersedes http://lists.freedesktop.org/archives/mesa-dev/2010-July/001442.html.
 2010-07-22 11:10:11 -04:00
Eric Anholt
c686ee0fa7 i965: In the VS, multiply the address reg by the appropriate register size. 
The ARL value is increments of vec4 in the register file.  But
PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved
between the two verts being executed (thus a vec8 each), compared to
PROGRAM_STATE_VAR being packed vec4s.

Fixes:
glsl-vs-arrays-2
glsl-vs-mov-after-deref
(without regressing glsl-vs-arrays-3)
 2010-07-21 22:05:30 -07:00
Eric Anholt
21eaa62ba4 i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support. 2010-07-21 20:17:24 -07:00
Eric Anholt
96b11f1e3e i965: Support relative addressed VS constant reads using the appropriate msg. 
The previous support was overly complicated by trying to use the same
1-OWORD message for both offsets.
 2010-07-21 20:17:24 -07:00
Eric Anholt
9e9e87a9b2 i965: Fix the DP read msg_control definitions other than plain OWORD. 2010-07-21 20:17:24 -07:00
Eric Anholt
d0326e0e4e i965: Clean up dead code from the VS get_constant/get_reladdr_constant split. 2010-07-21 20:17:24 -07:00
Eric Anholt
04de6861c1 i956: Set the execution size correctly for scratch space writes. 
Otherwise, the second half isn't written, and we end up reading back
black.

Fixes the remaining junk drawn in glsl-max-varyings, and will likely
help with a number of large real-world shaders.
 2010-07-21 20:17:24 -07:00
Eric Anholt
ff81a1dd92 i965: Set the GEM domain flags for the scratch space. 
They go into the render cache, so while we don't care about their
contents after execution, failing to note them could cause the writes
to be flushed over important buffer contents later.
 2010-07-21 20:17:24 -07:00
Eric Anholt
a3bfb2f755 i965: Use the pretty define for 4-oword DP reads. 2010-07-21 20:17:24 -07:00
Eric Anholt
d2f3eac8ff i965: Set the send commit bit on register spills as required pre-gen6. 
Otherwise, the subsequent read may not get the written value.
 2010-07-21 20:17:24 -07:00
Eric Anholt
0ecf5128a4 i965: Add disasm for dataport reads (register unspilling). 2010-07-21 20:17:24 -07:00
Kristian Høgsberg
7a66e54958 glx: Move last few dri_interface.h types out of glxclient.h and drop include 2010-07-21 22:17:24 -04:00
Kristian Høgsberg
f679640868 glx: Move __driContext field out of __GLXcontextRec 2010-07-21 22:17:24 -04:00
Brian Paul
7cd6a6cc99 softpipe: add missing support for PIPE_FORMAT_S8_USCALED surfaces 
And remove checks of surface depth bits.  The state tracker should
not turn on depth/stencil testing if the framebuffer doesn't have
depth/stencil.
 2010-07-21 16:52:01 -06:00
Brian Paul
ef2d10cd45 softpipe: fix sp_tile_cache_flush_clear() regression 2010-07-21 16:00:52 -06:00
Jerome Glisse
600c85efdb Revert "dri2: Remove an unused variable." 
glx_info is used if X_DRI2SwapBuffers is defined
This reverts commit c0ca2bfb2a.
 2010-07-21 17:40:37 -04:00
Jerome Glisse
0bca8fbfda r600g: add support for all R6XX/R7XX asic 
This configure some of the value properly based on
asic so others asic than RV710 works too.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
 2010-07-21 17:05:37 -04:00