Commit graph

60043 commits

Author SHA1 Message Date
Chris Forbes
a1ca580240 i965: Don't flag gather quirks for Gen8+
My understanding is that Broadwell retains the same SCS mechanism
that Haswell has, so even if the underlying issue with this format
is not fixed, the w/a will be applied in SCS rather than needing
shader code.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-07 16:17:27 +13:00
Chris Forbes
83b83fb984 i965/Gen7: Allow CMS layout for multisample textures
Now that all the pieces are in place, this should provide
a nice performance boost for apps using multisample textures.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-07 16:10:04 +13:00
Chris Forbes
3122c2421a i965/vs: Sample from MCS surface when required
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-07 16:10:02 +13:00
Chris Forbes
7810162053 i965/fs: Sample from MCS surface when required
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-07 16:09:49 +13:00
Chris Forbes
7629c489c8 i965: Add shader opcode for sampling MCS surface
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-07 16:09:32 +13:00
Chris Forbes
27359b8079 i965/Gen7: Include bitfield in the sampler key for CMS layout
We need to emit extra shader code in this case to sample the
MCS surface first; we can't just blindly do this all the time
since IVB will sometimes try to access the MCS surface even if
disabled.

V3: Use actual MSAA layout from the texture's mt, rather
then computing what would have been used based on the format.
This is simpler and less fragile - there's at least one case where
we might want to have a texture's MSAA layout change based on what
the app does (CMS SINT falling back to UMS if the app ever attempts
to render to it with a channel disabled.)

This also obsoletes V2's 1/10 -- compute_msaa_layout can now remain
an implementation detail of the miptree code.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-07 16:09:12 +13:00
Chris Forbes
b1604841c2 i965/Gen7: Move decision to allocate MCS surface into intel_mipmap_create
This gives us correct behavior for both renderbuffers (which previously
worked) and multisample textures (which would never get an MCS surface
allocated, even if CMS layout was selected)

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-07 16:08:55 +13:00
Chris Forbes
6ca9a6f4d7 i965/Gen7: emit mcs info for multisample textures
Previously this was only done for render targets.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-07 16:08:52 +13:00
Chris Forbes
dfa952da97 i965/wm: Set copy of sample mask in 3DSTATE_PS correctly for Haswell
The bspec says:

"SW must program the sample mask value in this field so that it matches
with 3DSTATE_SAMPLE_MASK"

I haven't observed this to actually fix anything, but stumbled across it
while adding the rest of the support for CMS layout for multisample
   textures.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-07 16:08:47 +13:00
Chris Forbes
8064b0f2c4 i965: refactor sample mask calculation
Haswell needs a copy of the sample mask in 3DSTATE_PS; this makes that
convenient.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-07 16:07:53 +13:00
Ian Romanick
758658850b glsl: Don't emit empty declaration warning for a struct specifier
The intention is that things like

   int;

will generate a warning.  However, we were also accidentally emitting
the same warning for things like

  struct Foo { int x; };

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68838
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Aras Pranckevicius <aras@unity3d.com>
Cc: "9.2 10.0" <mesa-stable@lists.freedesktop.org>
2013-12-06 08:06:54 -08:00
Thomas Hellstrom
453651e521 st/xa: Bump major version number to 2
For some reason this was left out when the version was changed...

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2013-12-06 06:18:03 -08:00
Ben Skeggs
92ceb327ba nvc0: fixup gk110 and up not being listed in various switch statements
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-12-06 11:28:45 +10:00
Kenneth Graunke
26f3ff8a91 i965: Replace non-standard INLINE macro with "inline".
These are identical: main/compiler.h defines INLINE to "inline".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-05 13:59:18 -08:00
Kenneth Graunke
11d9af7c0a i965: Don't use GL types in files shared with intel-gpu-tools.
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
       -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
       -e 's/GLshort/int16_t/g' \
       brw_eu* brw_disasm.c brw_structs.h

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-05 13:59:18 -08:00
Kenneth Graunke
a7bdd4cba8 i965: Drop trailing whitespace from the rest of the driver.
Performed via:
$ for file in *; do sed -i 's/  *//g'; done

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-05 13:59:18 -08:00
Kenneth Graunke
d542c45c75 i965: Drop trailing whitespace from files shared with intel-gpu-tools.
Performed via s/  *$//g.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-05 13:59:18 -08:00
José Fonseca
3be333ed30 tools/trace: More tweaks to state dumping.
- Ignore buffer format (it is totally arbitrary)
- Initialize state.
- Handle begin/end_query statements.
2013-12-05 13:35:06 +00:00
José Fonseca
9648b76dc4 trace: Reorder dumping of pipe_rasterizer_state.
Such that it matches the pipe_rasterizer_state declaration, making it
easier to double-check that all state is being actually dumped.

Trivial.
2013-12-05 13:35:06 +00:00
José Fonseca
10450cbbe6 trace: Dump pipe_sampler_state::seamless_cube_map.
Trivial.
2013-12-05 13:35:06 +00:00
Michel Dänzer
7435d9f77c radeonsi: Remove some stale XXX / FIXME comments
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-05 13:50:07 +09:00
Matt Turner
cbb49cb2f7 i965: Emit better code for ir_unop_sign.
total instructions in shared programs: 1550449 -> 1550048 (-0.03%)
instructions in affected programs:     15207 -> 14806 (-2.64%)

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-12-04 20:05:44 -08:00
Matt Turner
d30b2ed5f8 i965/fs: New peephole optimization to flatten IF/BREAK/ENDIF.
total instructions in shared programs: 1550713 -> 1550449 (-0.02%)
instructions in affected programs:     7931 -> 7667 (-3.33%)

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-04 20:05:44 -08:00
Matt Turner
9658b04fc4 i965/fs: Emit a MOV instead of a SEL if the sources are the same.
One program affected.

instructions in affected programs:     436 -> 428 (-1.83%)

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-04 20:05:44 -08:00
Matt Turner
4532cac06a i965/fs: Extend SEL peephole to handle only matching MOVs.
Before this patch, the following code would not be optimized even though
the first two instructions were common to the then and else blocks:

   (+f0) IF
   MOV dst0 ...
   MOV dst1 ...
   MOV dst2 ...
   ELSE
   MOV dst0 ...
   MOV dst1 ...
   MOV dst3 ...
   ENDIF

This commit extends the peephole to handle this case.

No shader-db changes.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:44 -08:00
Matt Turner
13de9f03f1 i965/fs: New peephole optimization to generate SEL.
fs_visitor::try_replace_with_sel optimizes only if statements whose
"then" and "else" bodies contain a single MOV instruction. It also
could not handle constant arguments, since they cause an extra MOV
immediate to be generated (since we haven't run constant propagation,
there are more than the single MOV).

This peephole fixes both of these and operates as a normal optimization
pass.

fs_visitor::try_replace_with_sel is still arguably necessary, since it
runs before pull constant loads are lowered.

total instructions in shared programs: 1559129 -> 1545833 (-0.85%)
instructions in affected programs:     167120 -> 153824 (-7.96%)
GAINED:                                13
LOST:                                  6

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-04 20:05:44 -08:00
Matt Turner
fa227e7cbc i965/fs: Add SEL() convenience function.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-04 20:05:43 -08:00
Matt Turner
4b0ef4bf38 glsl: Use fabs() on floating point values.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-04 20:05:43 -08:00
Matt Turner
8814806c97 i965: Print conditional mod in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:43 -08:00
Matt Turner
b9af66528e i965: Externalize conditional_modifier for use in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:43 -08:00
Matt Turner
637dda1c30 i965: Print argument types in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:43 -08:00
Matt Turner
21e92e74c8 i965: Externalize reg_encoding for use in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:43 -08:00
Matt Turner
729fe77e3b i965/vec4: Don't print swizzles for immediate values.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:43 -08:00
Matt Turner
2b8e0a73fb i965/vec4: Print negate and absolute value for src args.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:43 -08:00
Matt Turner
a85f1b7adf i965/vec4: Add support for printing HW_REGs in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:43 -08:00
Matt Turner
942151af30 i965/fs: Print ARF registers properly in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:43 -08:00
Matt Turner
0e4053234d i965: Don't print extra (null) arguments in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
d79e711718 glsl: Remove silly OR(..., 0x0) from ldexp() lowering.
I translated copysign(0.0f, x) a little too literally.

Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
b1eb2ad8d1 i965: Allow commuting the operands of ADDC for const propagation.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
04d83396ee i965/fs: Rename register_coalesce_2() -> register_coalesce().
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
9a6b14f674 i965/fs: Remove now useless register_coalesce() pass.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
1520ae48b8 i965/fs: Let register_coalesce_2() eliminate self-moves.
This is the last thing that register_coalesce() still handled.

total instructions in shared programs: 1561060 -> 1560908 (-0.01%)
instructions in affected programs:     15758 -> 15606 (-0.96%)

Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
8786f381ec i965: Allow constant propagation into ASR and BFI1.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
ba84800275 i965/cfg: Document cur_* variables.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
7642c3c6ff i965/cfg: Remove ip & cur from brw_cfg.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
d2fcdd0973 i965/cfg: Clean up cfg_t constructors.
parent_mem_ctx was unused since db47074a, so remove the two wrappers
around create() and make create() the constructor.

Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
c6450fa963 i965/cfg: Throw out confusing make_list method.
make_list is just a one-line wrapper and was confusingly called by
NULL objects. E.g., cur_if == NULL; cur_if->make_list(mem_ctx).

Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
f3bce19f6c i965/cfg: Include only needed headers.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:42 -08:00
Matt Turner
f4b50a1466 i965/cfg: Remove unnecessary endif_stack.
Unnecessary since last commit.

Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:41 -08:00
Matt Turner
2eb9bbfb68 i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.

This should be immaterial to dataflow analysis, except for if, break,
endif sequences:

   START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8)     null            g15<8,8,1>F     g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0                 null            0x00000000UD
   END B1 ->B2 ->B4
   START B2 <-B1
   break
0x00000120: break(8) 0 0                    null            0D
   END B2 ->B10
   START B3
0x00000130: endif(8) 2                      null            0x00000002UD
   END B3 ->B4

The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.

This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.

It helps three programs (including two fs8/fs16 pairs).

total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs:     837 -> 771 (-7.89%)

More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.

Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-04 20:05:41 -08:00