Commit graph

84732 commits

Author SHA1 Message Date
Topi Pohjolainen
a1c7de09dc intel/blorp: Add plumbing for setting color clear layer count
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 11:48:29 +03:00
Topi Pohjolainen
514afdce95 intel/blorp: Allow multiple layers
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 11:48:29 +03:00
Topi Pohjolainen
e597821ef2 i965/blorp: Instruct vertex fetcher to provide prim instance id
This will indicate target layer (Render Target Array Index) needed
for layered clears.

v2: Use 3DSTATE_VF_SGVS for gen8+

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 11:48:29 +03:00
Topi Pohjolainen
39712b2a14 i965/rbc: Allocate mcs directly
such as we do for compressed msaa. In case of non-compressed simgle
sampled buffers the allocation of mcs is deferred until there is
actually a clear operation that needs the mcs.
In case of render buffer compression the mcs buffer always needed
and there is no real reason to defer the allocation. By doing it
directly allows to drop quite a bit unnecessary complexity.

Patch leaves brw_predraw_set_aux_buffers() a no-op. Subsequent
patches will re-use it and it seemed cleaner to leave it instead
of removing and re-introducing.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 11:48:29 +03:00
Topi Pohjolainen
024a39511f isl/gen8+: Allow 1D and 3D auxiliary surfaces
Otherwise once mcs buffer gets allocated without delay for lossless
compression (same as we do for msaa), assert starts to fire in
piglit case: tex3d. The test uses depth of one which is in fact
supported even now.

v2 (Jason): Allow also 1D case as there is nothing in the specs
            constraining it either.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 11:48:29 +03:00
Topi Pohjolainen
6939532593 i965: Add sanity check for non-compressible texture views
v2: Fix missing inline declaration

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 11:48:29 +03:00
Topi Pohjolainen
1b6fcc08df i965/rbc: Consult rb settings for texture surface setup
Once mcs buffer gets allocated without delay for lossless
compression (same as we do for msaa), one gets regression in:

GL45-CTS.texture_barrier_ARB.same-texel-rw

Setting the auxiliary surface for both sampling engine and data
port seems to fix this. I haven't found any hardware documentation
backing this though.

v2 (Jason): Prepare also for the case where surface is sampled with
            non-compressible format forcing also rendering without
            compression.
v3: Split asserts and decision making.
v4: Detailed comment provided by Jason explaining the need for using
    auxiliary buffer for texturing when the same surface is also
    used as render target.
    Added check for existence of renderbuffer before considering if
    underlying miptree matches.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 11:46:13 +03:00
Topi Pohjolainen
22d9a4824b i965: Track non-compressible sampling of renderbuffers
v3:
   - Actually set the flags when needed instead of falsely
     overwriting them (Jason).
   - Use more generic name for flag (dropped RENDERBUFFER)
   - Consult also shader images
v4:
   - Consult only lossless compressd shader images

v5:
   - Check the existence of renderbuffer before considering
     if it matches the given miptree

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 08:58:38 +03:00
Topi Pohjolainen
1f51217d99 i965: Replace boolean rb surface state setup argument with flags
And add plumbing to provide it all the way to surface state emitter.
This is not used yet but will be in subsequent patches to carry
additional constraints.

v2 (Jason): Use uint32_t instead of int as the type

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 08:58:38 +03:00
Topi Pohjolainen
1634a4963c i965/rbc: Allow integer formats as advertised in isl_format.c
Blorp consults brw_is_color_fast_clear_compatible() to see if any
restrictions apply for fast clear in addition to the capablities
advertised in isl_format.c::format_info[]. On Gen8+ integer formats
are backlisted for plain old fast clear but there is no reason why
lossless compression shouldn't be supported. In fact, lossless
compression of integer formats is already supported for normal
render paths.

This patch prepares for dropping the delayed allocating of the mcs
buffer for lossless compression. Until now the skip of fast clear
also prevented the mcs being allocated and hence the lossless
compression being effectively turned off for integer formats.
Once the mcs buffer is allocated beforehand, the assertion addressed
here would start triggering.

v2: Drop the assert instead of relaxing it (Jason)
    Fix typo while at it.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 08:58:38 +03:00
Alejandro Piñeiro
e77bf32475 i965: remove unused variable at intel_miptree_create_for_teximage
After commit "i965: Fix calculation of the image height at start level", it is
not needed. This commit removes the "warning: unused variable ‘i’" warning.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 07:21:32 +02:00
Thomas Helland
08c5b10ae9 mesa/glsl: Move string_to_uint_map into the util folder
This clears the last bits of the usecases of the hash table
located in mesa/program, allowing us to remove it.

V2: Rebase on top of changes to Makefile.sources

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
e55eb2b7ea glsl: Convert glcpp-parse to the util hash table
And change the include in glcpp.h accordingly.

V2: Whitespace fix

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
16fb318d0c glsl: Convert loop analysis to the util hash table
Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
ec453979db mesa: Convert symbol table to the util hash table
Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
f224ef4392 glsl: Convert varying test to the util hash table
V2: remove now unused ht_count_callback() (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
9efa977be5 glsl: Convert output read lowering to the util hash table
Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
6adcc8f283 glsl: Convert interface block lowering to the util hash table
V2: move comment to correct location (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
5482d31b86 glsl: Convert if lowering to use a set
Also do some minor whitespace cleanups

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
85a197c4ed glsl: Convert linker to the util hash table
We are getting the util hash table through the include in
program/hash_table.h for the moment until we migrate the
string_to_uint_map to a separate file.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
f10cc9407b glsl: Convert link_varyings to the util hash table
Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
e7f91d9de1 glsl: Change link_functions to use a set
The "locals" hash table is used as a set, so use a set to
avoid confusion and also spare some minor memory.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
2228548f83 glsl: Convert recursion detection to the util hash table
Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
9b3c0f81a7 glsl: Convert constant_expression to the util hash table
V2: Fix incorrect ordering on hash table insert

V3: null check value returned by _mesa_hash_table_search()
    (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
9f188be8a6 glsl: Convert ast_to_hir to the util hash table
V2: Rebase to the adaption of new hashing functions

V3: move previous_label declaration to where it is used
    (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
9ac6d61751 glsl: Convert ir_clone to the util hash table
V2: add braces to multiline if (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
5b5d4ea4a0 glsl: Convert function inlining to the util hash table
Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
eef2be6822 mesa: Convert string_to_uint_map to the util hash table
And remove the now unused hash_table_replace.

V2: Actually do the equivalent thing, and don't leak memory

V3: fix minor typo in comment (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
ddb8639b18 util: Move hash_table_call_foreach to util hash table
It is included through the util/hash_table include in
the program hash_table, so this should be safe.
This will be needed when we start converting each use of
the program_hash_table, as some places need this function.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
cf4a4820ac mesa: Remove prog_hash_table.c
Here we make the prog_hash_table functionally equivalent to
the one in util by wrapping the remaing functions that differ.

We also move the functions to the header so we can remove the c
file.

This enables us to do a step-by-step replacement of the table.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Thomas Helland
42ba435fd1 mesa: Remove unused hash table includes
This should prevent us from rebuilding the world.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-12 10:48:35 +10:00
Ilia Mirkin
148fbf32a8 freedreno/a3xx: disable filtering for texture buffers and int textures
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-11 13:14:06 -04:00
Niels Ole Salscheider
cfa914a1b4 st/clover: Define __OPENCL_VERSION__ on the device side
This is required by the OpenCL standard.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
2016-09-10 15:48:54 -07:00
Ilia Mirkin
a8c0c7301c gm107/ir: allow indirect inputs to be loaded by frag shader
Looks like the GM107 IPA op does not allow a separate offset when
using an indirect register. Instead we must use AL2P like we do for
indirect vertex operations on Kepler+.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-09-10 13:40:04 -04:00
Ilia Mirkin
a22aee5ad1 gm107/ir: AL2P writes to a predicate register
We have to force it to write to predicate 7 (aka PT) in order for it not
to mess up another predicate. Unclear what would be returned in the
predicate, perhaps an error code for out-of-bounds requests. Blob
doesn't seem to check it.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2016-09-10 13:36:20 -04:00
Antia Puentes
83e8617f4b i965: Fix calculation of the image height at start level
- Fixes CTS tests:

* GL44-CTS.shader_image_size.advanced-nonMS-cs-float
* GL44-CTS.shader_image_size.advanced-nonMS-cs-int
* GL44-CTS.shader_image_size.advanced-nonMS-cs-uint
* GL44-CTS.shader_image_size.advanced-nonMS-gs-float
* GL44-CTS.shader_image_size.advanced-nonMS-gs-int
* GL44-CTS.shader_image_size.advanced-nonMS-gs-uint
* GL44-CTS.shader_image_size.advanced-nonMS-tes-float
* GL44-CTS.shader_image_size.advanced-nonMS-tes-int
* GL44-CTS.shader_image_size.advanced-nonMS-tes-uint
* GL44-CTS.shader_image_size.advanced-nonMS-vs-float
* GL44-CTS.shader_image_size.advanced-nonMS-vs-int
* GL44-CTS.shader_image_size.advanced-nonMS-vs-uint

v1: (written by Dave Airlie) Always shift height images for levels.
Fixed the CTS test.

v2: Only shift height if the texture is not an 1D_ARRAY,
it fixes assertion in GL44-CTS.texture_view.gettexparameter
due to the original patch (Antia).

v3: Remove the loop. Do not shift height either for 1D textures.
Use an explicit switch and add an assertion (levels == 0) for
multisampled textures (Jason).

v4: Rectangle textures can not have levels either (Ilia Mirkin).

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Antia Puentes <apuentes@igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-10 12:52:32 +02:00
Marek Olšák
08bcbfdc07 radeonsi: flush TC L2 before using a compute indirect buffer
There is no known test for this.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-09 22:45:07 +02:00
Marek Olšák
a5a2cc530c radeonsi: fix the VGT performance tweak for small instances
Based on the VGT spec.

The Vulkan driver doesn't do it optimally and they plan to fix it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-09 22:45:06 +02:00
Marek Olšák
a67d81580b radeonsi: remove the cache_flush atom
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-09 22:45:06 +02:00
Marek Olšák
f9750932ea winsys/amdgpu: replace OUT_CS with radeon_emit
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-09 22:45:06 +02:00
Marek Olšák
81da78bfc3 winsys/radeon: replace OUT_CS with radeon_emit
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-09 22:45:06 +02:00
Christoph Haag
55ba5fa9a6 doc: document GALLIUM_DRIVER
v2: Add dot at end of sentence

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-09 09:24:28 +02:00
Haixia Shi
b1d636aa00 egl/android: Set EGL_MAX_PBUFFER_WIDTH and EGL_MAX_PBUFFER_HEIGHT
Set config attributes EGL_MAX_PBUFFER_WIDTH and EGL_MAX_PBUFFER_HEIGHT to
hard-coded non-zero values. These two attributes are required on Android.

v2: use _EGL_MAX_PBUFFER_WIDTH/HEIGHT from egldefines.h
    (based on discussion on the first version)

Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-09-09 07:51:04 +03:00
Tapani Pälli
478fbc2348 android: depend on libmesa_genxml from i965 Android.gen.mk
Static library dependency is required to pull the generated
XML headers into the generated C file.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-09-09 07:51:04 +03:00
Tapani Pälli
4542c7ed5f i965: release GLSL IR in LinkShader after it's not needed
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-09-09 07:51:04 +03:00
Tapani Pälli
2cd02e30d2 glsl: use hash instead of exec_list in copy propagation
This change makes copy propagation pass faster. Complete link time
spent in test case attached to bug 94477 goes down to ~400 secs from
over 500 secs on my HSW machine. Does not fix the actual issue but
brings down the total. No regressions seen in CI.

v2: do not leak hash_table structure

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-09-09 07:50:42 +03:00
Jason Ekstrand
175ac629be i965/fs: Fail the shader compile instead of asserting when we can't spill
Blorp doesn't handle spilling so we set allow_spilling to false in that
case.  The blorp 16x MSAA resolve shader spills in 16-wide but not 8-wide.
This commit makes it so that we fail the 16-wide compile and successfully
fall back to 8-wide instead of just assert-failing when trying to compile
the 16-wide shader.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-09-08 20:53:01 -07:00
Jason Ekstrand
88a2a2e053 nir/gcm: Add global value numbering support
Unlike the current CSE pass, global value numbering is capable of detecting
common values even if one does not dominate the other.  For instance, in
you have

if (...) {
   ssa_1 = ssa_0 + 7;
   /* use ssa_1 */
} else {
   ssa_2 = ssa_0 + 7;
   /* use ssa_2 */
}

Global value numbering doesn't care about dominance relationships so it
figures out that ssa_1 and ssa_2 are the same and converts this to

if (...) {
   ssa_1 = ssa_0 + 7;
   /* use ssa_1 */
} else {
   /* use ssa_1 */
}

Obviously, we just broke SSA form which is bad.  Global code motion,
however, will repair this for us by turning this into

ssa_1 = ssa_0 + 7;
if (...) {
   /* use ssa_1 */
} else {
   /* use ssa_1 */
}

This intended to eventually mostly replace CSE.  However, conventional CSE
may still be useful because it's less of a scorched-earth approach and
doesn't require GCM.  This makes it a bit more appropriate for use as a
clean-up in a late optimization run.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-08 20:53:01 -07:00
Jason Ekstrand
99ff4b3eb2 nir/gcm: Call nir_metadata_preserve
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-08 20:53:01 -07:00
Max Staudt
02675622b0 r300g: Set R300_VAP_CNTL on RSxxx to avoid triangle flickering
On the RSxxx chip series, HW TCL is missing and r300_emit_vs_state()
is never called.

However, if R300_VAP_CNTL is never set, the hardware (at least the
RS690 I tested this on) comes up with rendering artifacts, and
parts that are uploaded before this "fix" remain broken in VRAM.
This causes artifacts as in fdo#69076 ("triangle flickering").

It seems like this setup needs to happen at least once after power on
for 3D rendering to work properly. In the DDX with EXA, this happens in
RADEON_SWITCH_TO_3D() when processing an XRENDER Composite or an
Xv request. So playing back a video or starting a GTK+2 application
fixes 3D rendering for the rest of the session. However, this auto-fix
doesn't happen when EXA is not used, such as with GLAMOR or Wayland.

This patch ensures the register is configured even in absence of
the DDX's EXA module.

The register setting is taken from:
  xf86-video-ati  --  RADEONInit3DEngineInternal()
  mesa/src/mesa/drivers/dri/r300  --  r300EmitClearState()

Tested on RS690.

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Max Staudt <mstaudt@suse.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-09-09 13:30:47 +10:00