Commit graph

37184 commits

Author SHA1 Message Date
Karol Herbst
a0393010c4 nv50/ir: move common converter code in base class
v2: remove TGSI related bits

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
2019-03-17 10:33:28 +01:00
Karol Herbst
bb50cb66f0 nvc0: print the shader type when dumping headers
this makes debugging the shader header a little easier

Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-03-17 10:33:27 +01:00
Bas Nieuwenhuizen
213de3ea99 radeonsi: Remove implicit const cast.
Fixes: b9e02fe138 "gallium: add pipe_grid_info::last_block"
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-03-17 00:07:38 +01:00
Gert Wollny
9bb63e9a7c softpipe: Enable PIPE_CAP_MIXED_COLORBUFFER_FORMATS
It seems softpipe actually supports this. This change enables the
following piglits as passing without regressions in the gpu test set:

 gl-3.1-mixed-int-float-fbo
 gl-3.1-mixed-int-float-fbo int_second
 fbo-blending-format-quirks

Changes for deqp:

 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_none_none QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_none_rbo QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_none_tex QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_rbo_none QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_tex_none QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_none_none QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_none_rbo QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_none_tex QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_rbo_none QualityWarning -> Pass
 dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_tex_none QualityWarning -> Pass

 dEQP-GLES3.functional.fbo.completeness.samples.rbo0_rbo0_tex Fail -> Pass
 dEQP-GLES3.functional.fbo.completeness.samples.rbo0_tex_none Fail -> Pass
 dEQP-GLES3.functional.fbo.completeness.samples.rbo1_rbo1_rbo1 Fail -> Pass
 dEQP-GLES3.functional.fragment_out.random.* NotSupported -> Pass

 dEQP-GLES31.functional.shaders.builtin_functions.common.frexp.*_fragment Fail -> Pass
 dEQP-GLES31.functional.shaders.builtin_functions.common.frexp.*_vertex Fail -> Pass
 dEQP-GLES31.functional.shaders.builtin_functions.precision.frexp.*_fragment.* Fail -> Pass
 dEQP-GLES31.functional.shaders.builtin_functions.precision.frexp.*_vertex.* Fail -> Pass

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-03-15 19:04:05 +01:00
James Zhu
abfd572bd2 gallium/auxiliary/vl: Change weave compute shader implementation
Use 2D_ARRARY instead of RECT to fetch texels for weave compute
shader.

Problem 2,3: Fixed interpolation issue with weave de-interlace

Fixes: 9364d66cb7 (Add video compositor compute shader render)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109646
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Bruno Milreu <bmilreu@gmail.com>
2019-03-15 11:53:15 -04:00
James Zhu
a8ee07d83e gallium/auxiliary/vl: Change grid setting
Using draw area for grid setting instead of destination
buffer size.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Bruno Milreu <bmilreu@gmail.com>
2019-03-15 11:53:15 -04:00
James Zhu
998dca4dbb gallium/auxiliary/vl: Increase shader_params size
Increase shader_params size to pass sampler data to
compute shader during weave de-interlace.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Bruno Milreu <bmilreu@gmail.com>
2019-03-15 11:53:15 -04:00
Marek Olšák
b276e8358a omx: add a compute path in enc_LoadImage_common
Acked-by: Leo Liu <leo.liu@amd.com>
2019-03-15 11:53:08 -04:00
Marek Olšák
323e7be91c omx: clean up enc_LoadImage_common
- add *pipe
- add documentation

Acked-by: Leo Liu <leo.liu@amd.com>
2019-03-15 11:53:08 -04:00
Marek Olšák
b9e02fe138 gallium: add pipe_grid_info::last_block
The OpenMAX state tracker will use this.

RadeonSI is adapted to use pipe_grid_info::last_block instead of its
internal state.

Acked-by: Leo Liu <leo.liu@amd.com>
2019-03-15 11:53:08 -04:00
Alyssa Rosenzweig
1ea42894c7 panfrost/midgard: Implement fpow
We have a native op for this, which was just found in a disassembly --
so instead of lowering, use it!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:50:24 +00:00
Alyssa Rosenzweig
2eb65c2173 panfrost: Compute viewport state on the fly
Previously, we were caching this incorrectly; there's no real reason to
given how variable it is (sensitive to changes in viewport, framebuffer
dimensions, and scissors) and how cheap it is to recompute. So, just do
it on the fly each draw.

Fixes glmark-es2 -bshadow and -brefract.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:12 +00:00
Alyssa Rosenzweig
c6a725888f panfrost; Disable AFBC for depth buffers
For inexplicable reasons, the depth buffer is faster if kept as linear,
whereas the colour buffers are faster if AFBC. Given both code paths are
available, we'll choose the faster one of each (which also helps with
testing coverage).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:12 +00:00
Alyssa Rosenzweig
54e45d1d73 panfrost: Allocate extra data for depth buffer
It's not clear why the hardware "spills" a little bit, but if we don't
do this, we get MMU faults with linear depth buffers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:12 +00:00
Alyssa Rosenzweig
79e474fa46 panfrost: Comment spelling fix
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:12 +00:00
Alyssa Rosenzweig
8c26890ac2 panfrost/mfbd: Respect per-job depth write flag
While a depth buffer may be supplied, it only needs to be written to if
the depth writemask is set for any draw AND if the depth buffer is not
immediately invalidated (as is the case for scanout). This refactors
panfrost_job to provide a depth write requirement, which is now
implemented for MFBD depth buffers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:11 +00:00
Alyssa Rosenzweig
9bf6024c6b panfrost/mfbd: Implement linear depth buffers
This removes a clunky hack where the depth buffer was enabled during the
*clear*, instead of during depth buffer linking. That said, this does
not yet support writeback like AFBC depth buffers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:11 +00:00
Alyssa Rosenzweig
23e0135723 panfrost: Minor comment cleanup (version detection)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:11 +00:00
Alyssa Rosenzweig
c119c282af panfrost: Remove staging MFBD
Same idea as the previous commit, but for the MFBD this time instead of
the SFBD.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:11 +00:00
Alyssa Rosenzweig
d47f090738 panfrost: Remove staging SFBD for pan_context
The fragment framebuffer descriptor should not be a context entry;
rather, it should be constructed only at fragment time to keep analysis
tractable.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:11 +00:00
Alyssa Rosenzweig
9dd84db7a5 panfrost: Break out fragment to SFBD/MFBD files
This substantially cleans up the corresponding logic at the expense of a
bit of code duplication; nevertheless, it's a net win since otherwise
incompatible hardware code is mixed confusingly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-14 22:47:11 +00:00
Alyssa Rosenzweig
4d1a356a57 freedreno: Use shared drm_find_modifier util
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-14 22:43:08 +00:00
Alyssa Rosenzweig
dd12142e34 vc4: Use shared drm_find_modifier util
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-03-14 22:43:06 +00:00
Alyssa Rosenzweig
cca270bb03 v3d: Use shared drm_find_modifier util
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-03-14 22:42:51 +00:00
Kenneth Graunke
0c3adaad22 iris: Don't mutate box in transfer map code
Not mutating the boxes is arguably cleaner.

Split from a patch by Chris Wilson but reworked to use a pointer to the
original box rather than making a copy at all.
2019-03-13 23:31:51 -07:00
Gurchetan Singh
d6dc68e7b5 virgl: use uint16_t mask instead of separate booleans
This should save some space.

Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-13 22:58:22 +00:00
Rafael Antognolli
2b2b449dd1 iris: Enable auxiliary buffer support again
Now that we are properly resolving buffers before giving them to the
window system, let's enable aux support again.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-13 14:45:13 -07:00
Rafael Antognolli
1281368d02 iris: Convert RGBX to RGBA always.
In i965, we disable the use of RGBX formats, so the higher layers of
Mesa choose the equivalent RGBA format, and swizzle the alpha channel to
1.0.

However, Gallium won't do that. We need to explicitly convert it to
RGBA.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-13 14:45:13 -07:00
Rafael Antognolli
9159a5bbf8 iris: Add resolve on iris_flush_resource.
The flush_resource hook is supposedly called when the resource content
needs to be made visible to external (okay, that's pretty vague). For
instance, it gets called before a surface gets handled to the window
system. So we need to resolve it if it's not resolved yet.

v2 (Ken):
 - Check mod_info in iris_flush_resource instead of ISL_AUX_USAGE_NONE
 - Drop my old broken resolve code from iris_resource_get_handle() now
   that Rafael's got it hooked up in the right place.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-13 14:45:13 -07:00
Chris Wilson
97ad0efba0 iris: Use streaming loads to read from tiled surfaces
Always use the streaming load (since we know we have Broadwell+, all of
our target CPU support sse41) for reading back form the tiled surface
for mapping the resource. This means we hit the fast WC handling paths
on Atoms (without LLC), and for big Core (with LLC) using the streaming
load is no less efficient as we do not require the tiled buffer to be
pulled into the CPU cache.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-13 10:54:16 -07:00
Chris Wilson
797fb6c6ac iris: Use coherent allocation for PIPE_RESOURCE_STAGING
On !llc machines (Atoms), reading from a linear buffers is slow and so
copying from one resource into the linear staging buffer is still slow.
However, we can tell the GPU to snoop the CPU cache when reading from and
writing to the staging buffer eliminating the slow uncached reads.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-13 10:54:16 -07:00
Chris Wilson
01b224047b iris: Use PIPE_BUFFER_STAGING for the query objects
We prefer fast CPU access to read back the query results.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-13 10:54:16 -07:00
Tomeu Vizoso
56e04f67f9 panfrost: Set bo->gem_handle when creating a linear BO
So we can free it later.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-13 07:35:39 +01:00
Tomeu Vizoso
bfbad30543 panfrost: Set bo->size[0] in the DRM backend
So we can unmap it later.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-13 07:35:25 +01:00
Eric Anholt
486b181fd7 v3d: Fix leak of the renderonly struct on screen destruction.
This makes v3d match vc4's destroy path.

Fixes: e113b21cb7 ("v3d: Add renderonly support.")
2019-03-12 16:15:40 -07:00
Eric Anholt
ccce940947 v3d: Disable PIPE_CAP_BLIT_BASED_TEXTURE_TRANSFER.
This reduces the runtime of dEQP-GLES3.functional.shaders.precision.* from
11.5s to 3.3s.  This brings CTS runs down to 4 hours on one of my target
devices.
2019-03-12 09:04:25 -07:00
Connor Abbott
1bbe58c214 radeonsi/nir: Use nir stripping pass
This reduces compilation time for my shader-db collection from around 40
seconds to 30, vs. 19 seconds for TGSI. There are still some shaders
that TGSI caches but NIR doesn't, partly because of more aggressive
cross-stage optimizations with NIR.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-03-12 10:49:48 +01:00
Sagar Ghuge
bbef6c2d5f iris: Flag fewer dirty bits in BLORP
v2: 1) Skip flagging IRIS_DIRTY_DEPTH_BUFFER if
       BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set (Kenneth Graunke)
    2) Add missing flags (Kenneth Graunke)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-11 22:46:39 -07:00
Alyssa Rosenzweig
587ad37e72 panfrost: Identify fragment_extra flags
The fragment_extra structure contains additional fields extending the
MRT framebuffer descriptor, snuck in between the main framebuffer
descriptor and the render targets. Its fields include those related to
transaction elimination and depth/stencil buffers. This patch identifies
the flags field (previously just "unk" with some magic values) as well
as identifying some (but not all) flags set by the driver.

The process of identifying flags brought a bug to light where
transaction elimination (checksumming) could not be enabled unless AFBC
was in-use. This issue is now resolved.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-03-12 02:37:42 +00:00
Alyssa Rosenzweig
e57ea53acf panfrost: Document "depth-buffer writeback" bit
This bit, if set, causes the depth buffer to be copied from GPU tile
memory to the provided depth buffer in main memory. If not set, the GPU
will not access the main memory (saving considerable memory bandwidth if
depth results are not actually used).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-12 02:37:42 +00:00
Alyssa Rosenzweig
2df4537f91 panfrost: Support linear depth textures
This combination has not yet been seen "in the wild" in traces, but to
support linear depth FBOs, ~bruteforce reveals this bit pattern is
necessary. It's not yet clear why the meanings of 0x1 and 0x2 are
essentially flipped (tiled vs linear for colour, linear vs some sort of
tiled for depth).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-03-12 02:37:41 +00:00
Alyssa Rosenzweig
9f25a4e65c panfrost: Allocate dedicated slab for linear BOs
Previously, linear BOs shared memory with each other to minimize kernel
round-trips / latency, as well as to work around a bug in the free_slab
function. These concerns are invalid now, but continuing to use the slab
allocator for BOs resulted in memory allocation errors. This issue was
aggravated, though not introduced (so not a real regression) in the
previous commit.

v2 (unreviewed): Fix bug in v1 preventing munmaps from working

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-03-12 02:37:41 +00:00
Alyssa Rosenzweig
f9dc1ebc0d panfrost: Determine framebuffer format bits late
Again, these formats are only properly known at the time of fragment job
emit. Rather than hardcoding the format, at least for MFBD we begin to
construct the format bits on-demand. This cleans up the code,
futureproofs for ES3 framebuffer formats, and should fix bugs regarding
FBO colour swizzles.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.visozo@collabora.com>
2019-03-12 02:37:41 +00:00
Alyssa Rosenzweig
7ba18cdfa9 panfrost: Delay color buffer setup
In an effort to cleanup framebuffer management code, we delay
colour buffer setup until the FRAGMENT job is actually emitted, allowing
the AFBC and linear codepaths to be unified.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.visozo@collabora.com>
2019-03-12 02:37:41 +00:00
Alyssa Rosenzweig
536bcaa68f panfrost: Combine has_afbc/tiled in layout enum
AFBC, tiled, and linear BO layouts are mutually exclusive; they should
be coupled via a single enum rather than ad hoc checks of booleans.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.visozo@collabora.com>
2019-03-12 02:37:41 +00:00
Alyssa Rosenzweig
d93c5c3148 panfrost: Cleanup needless if in create_bo
I'm not sure why we were checking for these additional criteria (likely
inherited from some other driver); remove the needless checks to cleanup
the code and perhaps fix some bugs down the line.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.visozo@collabora.com>
2019-03-12 02:37:41 +00:00
Brian Paul
ecb708fada gallium/winsys/kms: fix incomplete type compilation failure
Fixes:
../src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c: In function ‘kms_sw_displaytarget_from_handle’:
../src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c:402:60: error: dereferencing pointer to incomplete type ‘const struct pipe_resource’
                                                       templ->format,
                                                            ^

Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-03-11 20:08:16 -06:00
Brian Paul
04544d852c drisw: fix incomplete type compilation failure
Fixes:
../src/gallium/winsys/sw/dri/dri_sw_winsys.c: In function ‘dri_sw_displaytarget_display’:
../src/gallium/winsys/sw/dri/dri_sw_winsys.c:255:39: error: dereferencing pointer to incomplete type ‘struct pipe_box’
       offset = dri_sw_dt->stride * box->y;
                                       ^

Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-03-11 20:08:16 -06:00
Tomeu Vizoso
97f2d04d5e panfrost: Add support for PAN_MESA_DEBUG
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-12 00:30:27 +00:00
Tomeu Vizoso
f0b1bbebdd panfrost/midgard: Add support for MIDGARD_MESA_DEBUG
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-12 00:30:27 +00:00