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panfrost/midgard: Add support for MIDGARD_MESA_DEBUG

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Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Tomeu Vizoso 2019-03-08 15:04:50 +01:00 • committed by Alyssa Rosenzweig
parent c5236fc6e2
commit f0b1bbebdd
2 changed files with 50 additions and 22 deletions
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5
src/gallium/drivers/panfrost/midgard/midgard.h
View file

@ -30,6 +30,11 @@
#include <stdint.h>
#include <stdbool.h>
#define MIDGARD_DBG_MSGS 0x0001
#define MIDGARD_DBG_SHADERS 0x0002
extern int midgard_debug;
typedef enum {
midgard_word_type_alu,
midgard_word_type_load_store,

67
src/gallium/drivers/panfrost/midgard/midgard_compile.c
View file

@ -30,12 +30,14 @@
#include <stdio.h>
#include <err.h>
#include "main/mtypes.h"
#include "compiler/glsl/glsl_to_nir.h"
#include "compiler/nir_types.h"
#include "main/imports.h"
#include "compiler/nir/nir_builder.h"
#include "util/half_float.h"
#include "util/register_allocate.h"
#include "util/u_debug.h"
#include "util/u_dynarray.h"
#include "util/list.h"
#include "main/mtypes.h"
@ -47,6 +49,21 @@
#include "disassemble.h"
static const struct debug_named_value debug_options[] = {
{"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
{"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
DEBUG_NAMED_VALUE_END
};
DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
int midgard_debug = 0;
#define DBG(fmt, ...) \
do { if (midgard_debug & MIDGARD_DBG_MSGS) \
fprintf(stderr, "%s:%d: "fmt, \
__FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
/* Instruction arguments represented as block-local SSA indices, rather than
* registers. Negative values mean unused. */
@ -1041,7 +1058,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
}
default:
printf("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
assert(0);
return;
}
@ -1188,7 +1205,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
/* XXX */
if (!entry) {
printf("WARNING: Unknown uniform %d\n", offset);
DBG("WARNING: Unknown uniform %d\n", offset);
break;
}
@ -1332,7 +1349,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
emit_mir_instruction(ctx, fmul);
} else {
printf("Unknown input in blend shader\n");
DBG("Unknown input in blend shader\n");
assert(0);
}
} else if (ctx->stage == MESA_SHADER_VERTEX) {
@ -1341,7 +1358,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
ins.load_store.mask = (1 << instr->num_components) - 1;
emit_mir_instruction(ctx, ins);
} else {
printf("Unknown load\n");
DBG("Unknown load\n");
assert(0);
}
@ -1385,7 +1402,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
void *entry = _mesa_hash_table_u64_search(ctx->varying_nir_to_mdg, offset + 1);
if (!entry) {
printf("WARNING: skipping varying\n");
DBG("WARNING: skipping varying\n");
break;
}
@ -1420,7 +1437,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
_mesa_hash_table_u64_insert(ctx->ssa_varyings, reg + 1, (void *) ((uintptr_t) (offset + 1)));
}
} else {
printf("Unknown store\n");
DBG("Unknown store\n");
assert(0);
}
@ -1459,7 +1476,7 @@ midgard_tex_format(enum glsl_sampler_dim dim)
return TEXTURE_CUBE;
default:
printf("Unknown sampler dim type\n");
DBG("Unknown sampler dim type\n");
assert(0);
return 0;
}
@ -1502,7 +1519,7 @@ emit_tex(compiler_context *ctx, nir_tex_instr *instr)
}
default: {
printf("Unknown source type\n");
DBG("Unknown source type\n");
//assert(0);
break;
}
@ -1577,12 +1594,12 @@ emit_jump(compiler_context *ctx, nir_jump_instr *instr)
br.branch.target_break = ctx->current_loop;
emit_mir_instruction(ctx, br);
printf("break..\n");
DBG("break..\n");
break;
}
default:
printf("Unknown jump type %d\n", instr->type);
DBG("Unknown jump type %d\n", instr->type);
break;
}
}
@ -1616,7 +1633,7 @@ emit_instr(compiler_context *ctx, struct nir_instr *instr)
break;
default:
printf("Unhandled instruction type\n");
DBG("Unhandled instruction type\n");
break;
}
}
@ -1646,7 +1663,7 @@ dealias_register(compiler_context *ctx, struct ra_graph *g, int reg, int maxreg)
return REGISTER_UNUSED;
default:
printf("Unknown SSA register alias %d\n", reg);
DBG("Unknown SSA register alias %d\n", reg);
assert(0);
return 31;
}
@ -1731,8 +1748,8 @@ allocate_registers(compiler_context *ctx)
ins->ssa_args.src1 = find_or_allocate_temp(ctx, ins->ssa_args.src1);
ins->ssa_args.dest = find_or_allocate_temp(ctx, ins->ssa_args.dest);
}
print_mir_block(block);
if (midgard_debug & MIDGARD_DBG_SHADERS)
print_mir_block(block);
}
/* Let's actually do register allocation */
@ -1836,7 +1853,7 @@ allocate_registers(compiler_context *ctx)
ra_set_select_reg_callback(g, midgard_ra_select_callback, NULL);
if (!ra_allocate(g)) {
printf("Error allocating registers\n");
DBG("Error allocating registers\n");
assert(0);
}
@ -2285,7 +2302,7 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
/* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
if (register_dep_mask & written_mask) {
printf("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask, written_mask, register_dep_mask & written_mask);
DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask, written_mask, register_dep_mask & written_mask);
break;
}
@ -2570,7 +2587,7 @@ emit_binary_bundle(compiler_context *ctx, midgard_bundle *bundle, struct util_dy
}
default:
printf("Unknown midgard instruction type\n");
DBG("Unknown midgard instruction type\n");
assert(0);
break;
}
@ -2668,7 +2685,7 @@ embedded_to_inline_constant(compiler_context *ctx)
case midgard_alu_op_fcsel:
case midgard_alu_op_icsel:
case midgard_alu_op_isub:
printf("Missed non-commutative flip (%s)\n", alu_opcode_names[op]);
DBG("Missed non-commutative flip (%s)\n", alu_opcode_names[op]);
break;
/* These ops are commutative and Just Flip */
@ -2734,7 +2751,7 @@ embedded_to_inline_constant(compiler_context *ctx)
/* We don't know how to handle these with a constant */
if (src->abs || src->negate || src->half || src->rep_low || src->rep_high) {
printf("Bailing inline constant...\n");
DBG("Bailing inline constant...\n");
continue;
}
@ -3278,7 +3295,8 @@ emit_loop(struct compiler_context *ctx, nir_loop *nloop)
* now that we can allocate a block number for them */
list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
print_mir_block(block);
if (midgard_debug & MIDGARD_DBG_SHADERS)
print_mir_block(block);
mir_foreach_instr_in_block(block, ins) {
if (ins->type != TAG_ALU_4) continue;
if (!ins->compact_branch) continue;
@ -3364,6 +3382,8 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl
{
struct util_dynarray *compiled = &program->compiled;
midgard_debug = debug_get_option_midgard_debug();
compiler_context ictx = {
.nir = nir,
.stage = nir->info.stage,
@ -3491,7 +3511,9 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl
optimise_nir(nir);
nir_print_shader(nir, stdout);
if (midgard_debug & MIDGARD_DBG_SHADERS) {
nir_print_shader(nir, stdout);
}
/* Assign counts, now that we're sure (post-optimisation) */
program->uniform_count = nir->num_uniforms;
@ -3697,7 +3719,8 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl
program->blend_patch_offset = ctx->blend_constant_offset;
disassemble_midgard(program->compiled.data, program->compiled.size);
if (midgard_debug & MIDGARD_DBG_SHADERS)
disassemble_midgard(program->compiled.data, program->compiled.size);
return 0;
}