Compute clean tile state once at FB descriptor emission and use the
cached results to set the clean tile/pixel write enable flag on the RT
and Z/S/CRC descriptors and to retrieve whether any of the clean tile
write flags is set.
This commit now also prevents setting the clean tile/pixel write
enable flag on descriptors when the associated attachment is
discarded.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38422>
Previous commit makes rt_clear() and rt_clean_pixel_write() calls
directly from pan_emit_rt(). Move these function definitions
closer. This will also improve diffs of coming commits.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38422>
This simplifies the initialization of common flags by setting them
outside of the modifier handlers. This also makes it more consistent
with the depth/stencil config which uses the same technique.
Panfrost bitfield packed descriptors are most commonly pushed into
Non-Cacheable memory. For descriptors packed in more than one step
(e.g. to support various modifiers), it's important to avoid mixing
loads and stores on the same cacheline for best performance. This is
why pan_merge() is first called on stack allocated packed descriptors
before copying into a BO.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38422>
This only forces write-back of clean tiles when there's a clear.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38422>
Clean tiles must actually be written back for AFBC buffers (color,
z/s) when either one of the effective tile size dimension is smaller
than the superblock dimension. This commit fixes the current check
which compares the effective tile size to the superblock size.
Fixes: 762a0f4133 ("panfrost: Add the concept of render block")
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38422>
tu_CmdBeginRendering was unconditionally allocating a new
patchpoints_ctx. When resuming a render pass chain, this overwrote the
existing context from the suspended pass, leaking it and all associated
FDM patchpoints.
Fixes: 0dd06c74d6 ("tu: Fix FDM patchpoint memory leak")
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39639>
Avoiding NaNs should have the same effect but it's good practice to not
rely on float OPs for correctness.
Fixes: 95a89f7 ("radv: Report smaller bvh sizes when possible")
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39640>
For VS/TES/GS, we lower all outputs to temporaries and emit copies at the
end of the shader (or for GS, at each EmitVertex() call) from those
temporaries back to real outputs. We use vec8 URB writes without
writemasking, since our output area's contents are undefined anyhow.
This is simpler than what TCS and Mesh do, which allow for output
variables to be read/written at a per-component level at any time,
with the output memory being used for cross-thread communication.
Rather than using the complicated TCS/Mesh handling and relying on
vectorization, we port the emit_urb_writes() approach to NIR. This
also takes care of emitting the VUE header with default values when
fields aren't explicitly written by the shader.
We also handle multiview in the process. It simplifies things, and
also drops another case of non-semantic IO in brw.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39666>
The TES workaround code is still going to be needed even after
we rework URB output handling for VS/TES/GS to use NIR intrinsics.
For VS, we know at least one URB write will have been emitted at
the end of the program, so we can just tag it.
GS already handles EOT via emit_gs_thread_end().
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39666>
This lets us look up things in varying_to_slot[] without having to
special case VIEWPORT, LAYER, and PRIMITIVE_SHADING_RATE. All of them
map to the same slot as PSIZ, slot 0, the VUE header.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39666>
We'll need the VUE map when we convert to using URB intrinsics.
Prepare for that by reordering VUE map setup before IO lowering.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39666>
As seen in the Vivante kernel driver function gckHARDWARE_Flush(),
GPUs without gcvFEATURE_TEX_CACHE_FLUSH_FIX, which translates to
all GPUs before halti5, need a full stall of the GPU pipeline
before flushing the texture caches.
This fixes sporadic GPU hangs observed in use-cases where texture
data updates are intermixed with draws without any state changes
that might necessitate a stall.
Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39673>
For now this runs on anv and freedreno a618 -- other devices have manual
skips for it currently, or run under a compositor, or don't have a
connector with a mode that the tests are willing to use. Hopefully we can
extend coverage to other devices soon.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39568>
The implicit_unmap tests complete in ~18s each on my A740, so I think they
should be fine to remove from all devices' skips files -- the problem was
hitting swap in parallel.
This reshuffles some test groups, making new xfails show up. The changes
are particularly notable in virgl, where virglrenderer gets wedged at some
point, arbitrary sets of tests after that fail.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39568>
They're vector args in deqp-runner, you can just specify the arg multiple
times. This also means that the expectations.json will have the proper
filenames in it, rather than the fake one. Also cleans up
deqp-runner.sh's "set -x" output nicely.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39568>
These have been intermittently timing out on HDK8350/A660, showing up as
flakes (then the shader cache gets the re-run to pass, since there are
multiple shaders compiled per test). Extending the pre-merge skip set on
the other devices should also help tame our runtimes, giving us more room
for other important testing (vkd3d, KHR_display).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39568>
When you get UnexpectedResult(skip), that means take your xfail out
because it's now skipping. Which is the fix, instead of "take the xfail
out and add it to manual skips".
Fixes: e54440d15e ("Uprev Piglit to a3826de3c26a279599d15b018a9a3e75ca46f4f8")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39568>
