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brw: Implement load_urb_output_handle_intel for VS/GS stages

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Simply get the payload field.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39666>
This commit is contained in:
Kenneth Graunke 2026-01-05 16:07:00 -08:00 • committed by Marge Bot
parent 0cbf49aa8f
commit 2af44670ed
1 changed files with 8 additions and 0 deletions
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8
src/intel/compiler/brw/brw_from_nir.cpp
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@ -2688,6 +2688,10 @@ brw_from_nir_emit_vs_intrinsic(nir_to_brw_state &ntb,
case nir_intrinsic_load_base_vertex:
UNREACHABLE("should be lowered by nir_lower_system_values()");
case nir_intrinsic_load_urb_output_handle_intel:
bld.MOV(retype(dest, BRW_TYPE_UD), s.vs_payload().urb_handles);
break;
case nir_intrinsic_load_input: {
assert(instr->def.bit_size == 32);
const brw_reg src = offset(brw_attr_reg(0, dest.type), bld,
@ -3133,6 +3137,10 @@ brw_from_nir_emit_gs_intrinsic(nir_to_brw_state &ntb,
break;
}
case nir_intrinsic_load_urb_output_handle_intel:
bld.MOV(retype(dest, BRW_TYPE_UD), s.gs_payload().urb_handles);
break;
case nir_intrinsic_emit_vertex_with_counter:
emit_gs_vertex(ntb, instr->src[0], nir_intrinsic_stream_id(instr));