Commit graph

195114 commits

Author SHA1 Message Date
Tapani Pälli
0e02de5a50 iris: fix issues with memory object updates via glBufferSubData
Disable aysnc mapping in case we are updating a external memobj.

Fixes following Piglit tests:
   spec@ext_external_objects@vk-pix-buf-update-errors
   spec@ext_external_objects@vk-vert-buf-update-errors

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29303>
2024-09-17 10:06:58 +00:00
Lionel Landwerlin
02b124846f brw: fix TGM messages to use cmask lsc opcodes
This is a restriction for TGM.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b55f7716 ("intel/brw: Switch to emitting MEMORY_*_LOGICAL opcodes")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31199>
2024-09-17 09:28:58 +00:00
Lionel Landwerlin
2159e17da0 brw: remove (load|store)_raw_intel
Those are Elk specific intrinsics.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b8f264cfe4 ("intel/brw: Handle load/stores in lsc_op_for_nir_intrinsic()")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31199>
2024-09-17 09:28:58 +00:00
Pavel Ondračka
b3b09db951 r300/ci: update fails list with a recent fix
Since the atan NIR improvements in 8579375777 we can now fit into
the cruel 64 ALU instruction limit on RV370.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31197>
2024-09-17 09:03:09 +00:00
Samuel Pitoiset
656d7e887a radv: fix lowering the view index to an input varying for FS
When multiview is used and the FS is compiled separately with GPL, the
view index still needs to be lowered, otherwise it's crashing later.

The lowering doesn't need to know the previous stage because ViewIndex
is a global thing (ie. it's neither a per-vertex or a per-primitive
varying).

This fixes recent
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.other.view_index_from_device_index_*_pre_rasterization

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31192>
2024-09-17 06:36:08 +00:00
Samuel Pitoiset
fb3b563d1f radv: enable more properties with VK_KHR_maintenance5
They are all supported by the hw and this matches AMD drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31129>
2024-09-17 06:10:54 +00:00
Jesse Natalie
5b7e4f6ae7 driconf: Disable dzn for bg3.exe
The app selects dzn over native drivers in some instances and dzn
doesn't handle this app (yet), so disable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31157>
2024-09-17 00:12:22 +00:00
Jesse Natalie
28db11d2f3 winsys/d3d12: Implement the latency control option
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31157>
2024-09-17 00:12:22 +00:00
Jesse Natalie
e9ce526714 wgl: Add driconf options for controlling latency and swap interval
Latency is hooked up to a new winsys framebuffer interface method. Swap
interval replaces the previous environment variable. This does make the
environment variable lowercase but that seems worth the break to be able
to set it from driconf.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31157>
2024-09-17 00:12:22 +00:00
Jesse Natalie
64885821c2 winsys/d3d12: Use the waitable object to decrease latency
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31157>
2024-09-17 00:12:22 +00:00
Dylan Baker
2b8a980240 util/fossilize_db: don't use check_files_opened_successfully for foz_prepare
The check function will free the db or the file if the other is NULL,
however, in this case db and the file are passed to foz_destroy, which
will also free them. This results in a double free. Instead, check that
either is NULL, and then goto the error case to ensure proper cleanup.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29881>
2024-09-16 23:32:56 +00:00
Faith Ekstrand
112481d576 nil: Assert array_len == 0 in Extent4D<Bytes>::size_B()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31191>
2024-09-16 21:51:29 +00:00
Faith Ekstrand
7527b22fd6 nil: Return a more accurate size in level_size_B
This gives us the tightest bounds we can while still taking into account
all of the array and other strides.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31191>
2024-09-16 21:51:29 +00:00
Faith Ekstrand
1a50108e52 nil: Rework calculations of the sizes of miplevels
What we actually want here is the size of the 1/2/3D part of the level,
not the array part.  This means a little more code duplication but the
result is also way more clear.  This shouldn't be a functional change as
Extent4D<units::Bytes>::size_B() doesn't take array_len into account.

This means we no longer call Image::level_size_B() for layout. Instead,
Image::level_size_B() should mirror this code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31191>
2024-09-16 21:51:29 +00:00
Dylan Baker
99f1b7d732 compiler/glsl: explicitly delete copy constructor and copy-assign
Most of our visitors have custom destructors because they wrap C types,
and need to manually call destructors for those types. Because of this,
the implicitly generated copy constructors and copy-assignment operators
are not safe due copying pointers rather than data. Since we don't need
these features just delete them, so any attempt to use them would be a
compilation error. This doesn't fix any existing issue except stopping
coverity from complaining, but it does prevent new issues in the future.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29662>
2024-09-16 21:08:04 +00:00
Dylan Baker
3f3cb1e2fa intel/elk: delete copy constructor and copy-assignment-operator
To keep the rule-of-three. This points out that the implicit copy
operations would be dangerous when there is an explicit constructor and
destructor, since the class is holding un-managed memory.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29667>
2024-09-16 20:31:45 +00:00
Dylan Baker
5809209316 anv: enforce state->cmd_buffer is never null in emit_Simpler_shader_init_fragment
We have a couple of checks where we allow this to be NULL, but later we
unconditionally and unavoidably dereference the pointer, which means
there's no way that it ever could have been NULL. Change the assert at
the top to not allow NULL, and remove checks for it being NULL

CID: 1616544
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31156>
2024-09-16 19:16:58 +00:00
Dylan Baker
5ebdfc8813 anv: assert we don't write past the end of an array
Our array has a fixed size of 32, and we know at the start of the block
that our type_count is < 32, but in the loop we grow the block, in
theory up to 31 times. Coverity notes that, and points out we could
write off the end of the array. Add an assert in the loop to ensure we
don't, and to help Coverity out.

CID: 1615171
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31173>
2024-09-16 17:42:40 +00:00
Dylan Baker
7556521417 intel: replace (uint64_t - uint64_t) > 0 with uint64_t > uint64_t
As coverity points out, if the second uint64_t was greater than the
first (I don't think it actually can be), then the overflow would result
in the check succeeding when it shouldn't. We could cast this to an
integer type, but since we have uint64_t, we'd need int128_t for that.
Instead, replace the comparison to 0 with a direct comparison, since
that would give the correct result without potential to overflow.

CID: 1604833
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31175>
2024-09-16 17:12:17 +00:00
David Heidelberg
dfc4a68b0a ci/freedreno: re-enable piglit tests for Adreno 530 in nightly runs
Also, document recent Adreno 530 improvements and failures.

Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31183>
2024-09-16 16:30:33 +00:00
Rohan Garg
8b272c8d8c docs: update feature matrix for VK_KHR_shader_relaxed_extended_instruction
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30791>
2024-09-16 15:58:35 +00:00
Rohan Garg
854865a059 lvp: enable VK_KHR_shader_relaxed_extended_instruction
The extension only affects non semantic instructions that need no
handling in the backend compiler.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30791>
2024-09-16 15:58:35 +00:00
Rohan Garg
97f41bc819 v3dv: enable VK_KHR_shader_relaxed_extended_instruction
The extension only affects non semantic instructions that need no
handling in the backend compiler.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30791>
2024-09-16 15:58:35 +00:00
Rohan Garg
a03b307eea tu: enable VK_KHR_shader_relaxed_extended_instruction
The extension only affects non semantic instructions that need no
handling in the backend compiler.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Connor Abbott <cwabbott0@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30791>
2024-09-16 15:58:35 +00:00
Rohan Garg
85b8579bf6 radv: enable VK_KHR_shader_relaxed_extended_instruction
The extension only affects non semantic instructions that need no
handling in the backend compiler.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30791>
2024-09-16 15:58:35 +00:00
Rohan Garg
630656827f nvk: enable VK_KHR_shader_relaxed_extended_instruction
The extension only affects non semantic instructions that need no
handling in the backend compiler.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30791>
2024-09-16 15:58:35 +00:00
Rohan Garg
2a4fbce27a hk: enable VK_KHR_shader_relaxed_extended_instruction
The extension only affects non semantic instructions that need no
handling in the backend compiler.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30791>
2024-09-16 15:58:35 +00:00
Rohan Garg
daea7e1651 intel/compiler: use the correct cache enum for loads and stores
Fixes: 74efde7 ('intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*()')

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30742>
2024-09-16 15:18:31 +00:00
Rohan Garg
b99fd944e8 intel/compiler: version can never be above 11 due to the previous check
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30742>
2024-09-16 15:18:31 +00:00
Samuel Pitoiset
32567f6a2a radv: compute shader hash for shaders created without internal cache
VK_KHR_pipeline_binary allows the application to take full control on
the cache and internal caches (disk or in-memory) can be disabled.

Though the shader hash should still be computed, otherwise all pipeline
binaries have a key with all zeroes.

Fixes: 8802612458 ("radv: advertise VK_KHR_pipeline_binary"
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31163>
2024-09-16 13:53:36 +00:00
Samuel Pitoiset
ad68c83f92 radv: fix copying the pipeline binary key
Only the first byte was copied.

Fixes: be06bfcbed ("radv: add initial support for pipeline binaries")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31163>
2024-09-16 13:53:36 +00:00
Samuel Pitoiset
f88cf56087 radv/rt: skip shaders cache for pipelines created with the capture/replay flag
Otherwise, if a pipeline is found in cache it will use a different
shader arena for allocation and the capture replay shader group handles
won't match.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31188>
2024-09-16 12:29:49 +00:00
Hans-Kristian Arntzen
f3c6bbdd8d radv: Always make sure to write the pipeline binary key.
There's nothing in spec that says that key is only written
if data is also written.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: be06bfcbed ("radv: add initial support for pipeline binaries")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31162>
2024-09-16 11:38:07 +00:00
Ganesh Belgur Ramachandra
9aa9f7211e radeonsi: fix decode corruptions with AMD_IMAGE_OPCODES=false on non-CDNA based chips
This fix doesn't concern CDNA based chips such as gfx940 directly
but it fixes corruptions on other chips that use emulated image
loads and stores using buffers when AMD_IMAGE_OPCODES=false.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30891>
2024-09-16 09:31:49 +00:00
Ganesh Belgur Ramachandra
62592674e0 amd: fix incorrect PIPE_INTERLEAVE_BYTES size for CDNA chips
The expected PIPE_INTERLEAVE_BYTES size is ADDR_PIPEINTERLEAVE_256B on
gfx940 (or other CDNA based chips). Since CDNA based chips like gfx940
doesn't support image opcodes, it gets gibberish value from the kernel.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30891>
2024-09-16 09:31:49 +00:00
Pierre-Eric Pelloux-Prayer
ca41fa6a09 radeonsi/sqtt: don't store pipeline->bo in shader->bo
This is useless and causes hangs (eg: with Firefox).

Instead use a custom emit function for the sqtt state, and
add the pipeline BO to the buffer list at this point.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31171>
2024-09-16 08:50:33 +00:00
Pierre-Eric Pelloux-Prayer
a1408e9ad3 radeonsi/sqtt: don't leak the pipeline bo
Pass the reference from si_aligned_buffer_create directly
to pipeline instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31171>
2024-09-16 08:50:33 +00:00
Pierre-Eric Pelloux-Prayer
721ccd0292 radeonsi/sqtt: use XXH64_update
No functional change, but this is the way the XXH API is meant
to be used.

Also avoid setting the pipeline_code_hash twice.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31171>
2024-09-16 08:50:32 +00:00
Pierre-Eric Pelloux-Prayer
3ab34c5ffe radeonsi/sqtt: don't store the offsets in the pipeline
We can pass them to si_sqtt_register_pipeline / si_sqtt_add_code_object
directly instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31171>
2024-09-16 08:50:32 +00:00
Pierre-Eric Pelloux-Prayer
bda9e1f856 radeonsi: check the pointer before adding an offset
Otherwise callers can't detect errors.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31171>
2024-09-16 08:50:32 +00:00
Pierre-Eric Pelloux-Prayer
7fedd7e178 radeonsi: include the shader key in the sqtt pipeline hash
Otherwise we'll use the wrong shader if the key changed.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31171>
2024-09-16 08:50:32 +00:00
Pierre-Eric Pelloux-Prayer
27644af79b radeonsi/tests: allow to run radeonsi-run-tests.py with AMD_DEBUG
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31171>
2024-09-16 08:50:32 +00:00
Samuel Pitoiset
ba7e3be425 radv: merge radv_emit_epilog() with radv_emit_ps_epilog_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31150>
2024-09-16 07:53:00 +00:00
Samuel Pitoiset
26d8f1a306 aco,radv,radeonsi: move has_epilog to the fragment shader info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31150>
2024-09-16 07:53:00 +00:00
Samuel Pitoiset
b377ddfd04 radv,radeonsi: remove remaining occurrences of TCS epilog
TCS epilog has been removed few months ago.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31150>
2024-09-16 07:53:00 +00:00
David Rosca
e27eeff95d frontends/va: Remove fallback if app doesn't enable packed headers
This was only a best effort fallback and it doesn't always work.
Driver is expected to only output slice NALs when packed headers
are not enabled, so let's just do that.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31126>
2024-09-16 06:35:32 +00:00
David Rosca
d3429a7e00 radeonsi: Fix reported minimum width for video encode
Some apps would default to smaller resolutions than we currently report
as supported, despite the hardware being able to encode it. It's also
common for test apps/suites to use small resolutions.
libva-utils/h264encode uses 176x144 resolution by default and vulkan cts
have video clips with the same resolution too which would previously
fail to encode.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31109>
2024-09-15 14:22:29 +00:00
Marek Olšák
46b561b7cd radeonsi: fold si_improve_sync_flags logic into si_barrier_before_internal_op
This also implements the same thing for images.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
2024-09-14 11:03:45 -04:00
Marek Olšák
961c72d666 radeonsi: remove SI_OP_SYNC_CPDMA_BEFORE, always sync CP DMA
We want barriers to only consider compute as a possibility, and CP DMA
has to work with that, which means barriers can't have code specific
to CP DMA.

Always executing the CP DMA sync seems acceptable because CP DMA operations
are usually small, and CP DMA is almost never used on GFX10+.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
2024-09-14 11:03:45 -04:00
Marek Olšák
88eb1be2fc radeonsi: use si_barrier_{before,after}_internal_op for CP DMA
This makes the CP DMA code simpler and reuses the logic we use for internal
compute shaders.

The only thing that can't be handled in the barrier functions is
"!cp_dma_has_L2 -> SI_CONTEXT_INV_L2" because the barrier functions should
assume that only compute shader coherency is required to make them usable
everywhere, and the CP DMA code has to deal with it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
2024-09-14 11:03:45 -04:00