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intel/compiler: use the correct cache enum for loads and stores

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Fixes: 74efde7 ('intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*()')

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30742>
This commit is contained in:
Rohan Garg 2024-09-16 16:07:03 +02:00 • committed by Marge Bot
parent b99fd944e8
commit daea7e1651
1 changed files with 1 additions and 1 deletions
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src/intel/compiler/brw_lower_logical_sends.cpp
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@ -114,7 +114,7 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
LSC_DATA_SIZE_D32, dst_comps /* num_channels */,
false /* transpose */,
LSC_CACHE(devinfo, STORE, L1UC_L3UC));
LSC_CACHE(devinfo, LOAD, L1UC_L3UC));
/* Update the original instruction. */
inst->opcode = SHADER_OPCODE_SEND;