Commit graph

190082 commits

Author SHA1 Message Date
Rhys Perry
ce2be5ab8e aco: combine VALU lanemask hazard into VALUMaskWriteHazard
This is now basically the same as the original VALUMaskWriteHazard, except
it now considers both VALU and SALU writes.

Now that it's a part of VALUMaskWriteHazard, differences from the original
VALU lanemask workaround are:
- it includes SALU reads after the write
- it includes VALU writes and SALU/VALU reads after the write which are
  not lanemasks
- it combines s_waitcnt_depctr instructions when it's a read after both a
  SALU write and a VALU write
- non-exec VALU SGPR reads reset the SGPRs read by VALU as a lanemask
- exec SGPRs are ignored

resolve_all_gfx11() is also finished.

fossil-db (navi31):
Totals from 21538 (27.13% of 79377) affected shaders:
Instrs: 27628855 -> 27552972 (-0.27%); split: -0.30%, +0.03%
CodeSize: 145968448 -> 145667616 (-0.21%); split: -0.23%, +0.02%
Latency: 209537805 -> 209509519 (-0.01%); split: -0.02%, +0.00%
InvThroughput: 36304270 -> 36301624 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12623
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11480
Backport-to: 25.0
Backport-to: 25.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34529>
2025-04-17 17:28:22 +00:00
Mel Henning
eee3c8eab8 nak: Handle idp4 ureg latencies
Fixes: 6b8a4e6bb7 ("nak: Add Turing latency information")
Fixes: 7a01953a39 ("nak: Add Ampere and Ada latency information")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12993
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34563>
2025-04-17 17:10:40 +00:00
Mel Henning
de1ed48325 nak/spill_values: Spill constants across edges if needed
In a previous iteration of the spilling code, we added an extra check to
only spill across edges if the value being spilled is in the W set.
This was due to a misunderstanding of the modeling of S and W in Braun
and Hack.  In the current implementation, we maintain the invariant that
every live value is in at least one of S or W so we don't need that
check but it was left in by mistake.

One exception to this rule was added when we special-cased constant
values.  Now the invariant is that every live value is in S, in W, or is
a constant.  When we made this change, the check we accidentally left in
bit us because now if a value is constant but not in W, it wasn't
getting spilled across the edge.  This can result in a value getting
filled later which was never spilled, leading to undefined values.

Fixes: 7b82e26e3c ("nak: Don't spill/fill const values")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12993
Co-authored-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34563>
2025-04-17 17:10:40 +00:00
Rohan Garg
cbc1ec4f73 anv: re enable compression for CPS surfaces on platforms other than Xe
I accidentally disabled compression on CPS surfaces marked as storage or
color attachment for all platforms, when this should only be limited to
Xe.

Fixes: 80f9b6 ('anv: CPB surfaces that are used as color attachments or for stores cannot be compressed')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34297>
2025-04-17 14:24:11 +00:00
Rhys Perry
4fcf2eb1d7 aco/gfx12: VOPD src0/1 are src bank compatible if they are the same vgpr
fossil-db (gfx1201):
Totals from 66518 (83.80% of 79377) affected shaders:
Instrs: 36939667 -> 36656685 (-0.77%); split: -0.79%, +0.02%
CodeSize: 220575208 -> 220201764 (-0.17%); split: -0.21%, +0.04%
Latency: 258919732 -> 258137974 (-0.30%); split: -0.35%, +0.05%
InvThroughput: 49911351 -> 49643836 (-0.54%); split: -0.55%, +0.02%
VClause: 788661 -> 788430 (-0.03%); split: -0.04%, +0.01%
SClause: 1176416 -> 1176263 (-0.01%); split: -0.02%, +0.01%
VALU: 18014058 -> 17818119 (-1.09%); split: -1.10%, +0.01%
VOPD: 4926983 -> 5122922 (+3.98%); split: +4.01%, -0.04%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34246>
2025-04-17 14:00:29 +00:00
Rhys Perry
3446f2059d aco/gfx12: assume VOPD with two v_mov_b32 are src bank compatible
fossil-db (gfx1201):
Totals from 10576 (13.32% of 79377) affected shaders:
(no stats changed)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34246>
2025-04-17 14:00:29 +00:00
Rhys Perry
1bd5ae7b14 aco: refactor can_use_vopd so that it returns flags
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34246>
2025-04-17 14:00:29 +00:00
Rhys Perry
d4b418bbb9 aco: add are_src_banks_compatible helper for VOPD creation
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34246>
2025-04-17 14:00:29 +00:00
Rhys Perry
4b0da5b51f aco: rename is_opy_only to can_be_opx
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34246>
2025-04-17 14:00:29 +00:00
Rhys Perry
408fa33c09 aco/gfx12: don't use second VALU for VOPD's OPX if there is a WaR
fossil-db (gfx1201):
Totals from 38908 (49.02% of 79377) affected shaders:
Instrs: 30268107 -> 30268131 (+0.00%); split: -0.00%, +0.00%
CodeSize: 180843648 -> 180843640 (-0.00%); split: -0.00%, +0.00%
Latency: 224905962 -> 224906072 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 44322988 -> 44323004 (+0.00%)
VALU: 15124145 -> 15124167 (+0.00%)
VOPD: 4018504 -> 4018482 (-0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.0
Backport-to: 25.1
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34246>
2025-04-17 14:00:29 +00:00
Tomeu Vizoso
a9fde960e6 etnaviv/ml: Support FullyConnected with signed weights
Some checks are pending
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34545>
2025-04-17 13:30:21 +00:00
Tomeu Vizoso
9615d44d6e teflon: Skip unsupported FullyConvolution operations
Drivers don't support these combinations yet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34545>
2025-04-17 13:30:21 +00:00
Tomeu Vizoso
9409595c32 etnaviv/ml: All tensors are now 4D, adapt to it
After "teflon: Set unused dimensions to 1", all tensors have 4
dimensions, so change the dim index accordingly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34498>
2025-04-17 13:13:09 +00:00
Tomeu Vizoso
c728e73d65 etnaviv/ml: Track memory layout of tensors
Improve the decision on when to add transpose and detranspose jobs by
tracking the memory layout that a tensor is in.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34498>
2025-04-17 13:13:09 +00:00
Tomeu Vizoso
c4a5f8d665 teflon: Set unused dimensions to 1
So drivers don't need to superfluously watch out for zeroes when
multiplying among dimensions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34498>
2025-04-17 13:13:09 +00:00
Tomeu Vizoso
23ae1c3bff teflon: Actually accept concatenations with different number of channels
It is supported now by Etnaviv.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34498>
2025-04-17 13:13:09 +00:00
Tomeu Vizoso
bde0e69bcd etnaviv/ml: Consolidate transpose/detranspose
To simplify things, state that all operations as implemented expect
their input tensors to be in the channel order that the hardware
supports, and that the output tensors will be in that same order as
well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34498>
2025-04-17 13:13:09 +00:00
Tomeu Vizoso
e06265ed3a teflon: Only mark integers as signed
As these are the types that need special handling, eg. not
kTfLiteFloat32.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34498>
2025-04-17 13:13:09 +00:00
Samuel Pitoiset
209a0ede98 radv: add a function to emit meshlet registers on GFX11+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34518>
2025-04-17 12:49:47 +00:00
Samuel Pitoiset
836757bec3 radv: tidy up radv_emit_ps_epilog_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34518>
2025-04-17 12:49:47 +00:00
Samuel Pitoiset
dca35b7226 radv: tidy up radv_emit_geometry_shader()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34518>
2025-04-17 12:49:47 +00:00
Samuel Pitoiset
d999afeb7a radv: tidy up radv_emit_vertex_shader()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34518>
2025-04-17 12:49:47 +00:00
Samuel Pitoiset
85fdf69027 radv: simplify combining TES/VS+GS config registers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34518>
2025-04-17 12:49:47 +00:00
Samuel Pitoiset
0dd9833348 radv: remove redundant assertion when emitting PS epilog state
It's already checked by radv_emit_32bit_pointer().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34518>
2025-04-17 12:49:47 +00:00
Samuel Pitoiset
a230d2daa3 radv: use radeon_set_sh_reg() for only 1 DWORD
It's just shorter to write.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34518>
2025-04-17 12:49:47 +00:00
Antonio Ospite
4dabc7776f ci/android: show how to add more Android CTS test cases
Show how to add more Android CTS tests cases, using --include-filters

Only CtsNativeHardwareTestCases and CtsSkQPTestCases are actually
enabled for now, because the android-angle-lavapipe-cts job is part of
the pre-merge pipeline and these modules would not be too expensive to
run.

The container size increases by about 60Mb and the test time from 4m to
7 min on a local system, so it's an acceptable compromise to show how
multiple modules can be tested.

A similar mechanism will be used to add CtsDeqpTestCases tests in the
future, probably in nightly or weekly jobs, because that would require
more space in the containers and a lot more time to run the tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34479>
2025-04-17 11:50:07 +00:00
Samuel Pitoiset
11e8a96495 radv: use common scratch tmpring size programming
Some checks are pending
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No logical changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34549>
2025-04-17 10:35:40 +00:00
Samuel Pitoiset
710d7ea8b8 radv: compute the optimal scratch wavesize
This might increase the scratch BO sizes but it's supposed to be
faster because scratch waves would be distributed among memory channels.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34549>
2025-04-17 10:35:40 +00:00
Samuel Pitoiset
e433a57650 ac,radeonsi: rework computing scratch wavesize and tmpring register
To be re-used by RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34549>
2025-04-17 10:35:40 +00:00
Samuel Pitoiset
d94f8b4460 ac/gpu_info,radv: add scratch_wavesize_granularity info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34549>
2025-04-17 10:35:40 +00:00
Icenowy Zheng
82dda21806 zink: Do not use demote on IMG blobs
The implementation of demote in IMG blobs seems to be a piece of hack,
and the current use of it in Zink leads to assertion failure with
information "Uniflex does not support demote and terminate in the same
shader".

Disable usage of demote for IMG blobs.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33051>
2025-04-17 10:14:45 +00:00
Daniel Stone
8d08cde667 ci/piglit: Use structured tagging for Piglit
Structured tagging (cf. mesa/mesa!33421) captures a checksum of the
thing we think we're building, and verifies this through the chain.

When we run container builds, we check that the tag we've captured in
the CI variables matches the calculated checksum, to make sure the
declared tags are consistent and we always have traceability.

When we run tests, we check the tags again between what was declared in
the CI variables and what we're actually running from the test
container. This makes sure that we're always testing what we think we're
testing.

As a side advantage, the rule inheritance we need to make this work
means that we can start doing more optional downloads via overlays,
instead of pulling a whole container full of stuff we might not ever
use.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34539>
2025-04-17 09:22:39 +00:00
Samuel Pitoiset
e616761fb2 radv: re-introduce the compute vs CP DMA heuristic for copy/fill operations
Some checks are pending
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This caused a -5% performance regression in Control because using
compute always eats resources.

This new approach introduces a flag called RADV_COPY_FLAGS_DEVICE_LOCAL
which can be used to indicate if the underlying memory is device local.
This should also help for future work.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12639
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34556>
2025-04-17 08:59:58 +00:00
Samuel Pitoiset
5e2508e7c4 radv: simplify radv_fill_xxx() helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34556>
2025-04-17 08:59:58 +00:00
Samuel Pitoiset
8ba94d8263 radv: add radv_fill_image() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34556>
2025-04-17 08:59:58 +00:00
Samuel Pitoiset
0fa43b5bfb radv: use radv_fill_memory() in the accel struct path
It's now possible to remove the NULL BO check.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34556>
2025-04-17 08:59:58 +00:00
Tapani Pälli
6d70ec449f iris: make sure to not mix compressed vs non-compressed
Some checks are pending
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This commit implements the following requirement:

   "Keep any UMD-recycling of compression-enabled/disabled
    memory separate."

As additional info there are 2 related wa's for the issue:

   Wa_14018443005
   Wa_18038669374

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34499>
2025-04-17 06:17:53 +00:00
Tapani Pälli
c2a4657862 iris: force reallocate on eglCreateImage with GFX >= 20
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34499>
2025-04-17 06:17:53 +00:00
Tomeu Vizoso
aa73767f5e etnaviv/ml: Support per-channel quantized weights
Dequantize the weights, calculate new quantization values based on the
minimum and maximum values and requantize again.

This causes a loss of accuracy when compared to proper per-axis
quantization as we don't have the original data from training any more.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34497>
2025-04-17 05:25:49 +00:00
Philipp Zabel
ce9030740a teflon: Allow per-axis quantization
Allow per-axis quantization in the output channel dimension.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34497>
2025-04-17 05:25:49 +00:00
Tomeu Vizoso
7dfcca9007 etnaviv/ml: Fix zero point values for signedness
Take into account the signedness for FullyConnected.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34497>
2025-04-17 05:25:49 +00:00
Tomeu Vizoso
d88f0b8f3c etnaviv/ml: Reorder dimensions in convolutions
The blob does this, and doesn't seem to just be for performance as I see
some tests being fixed by it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34497>
2025-04-17 05:25:49 +00:00
Thomas H.P. Andersen
d55a69e769 nak: make is_fneg_zero detect -rZ
Some checks are pending
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fold_imm starts with this check:
        let SrcRef::Imm32(mut u) = self.src_ref else {
            return *self;
        };

For -rZ we thus return early and the matching in is_fneg_zero does not
find it. This MR adds a match for SrcRef::Zero + SrcMod::FNeg.

This lets copy propagation fold this:

r3  = shfl.bfly r2 0x2 0x1c03
r3  = fswzadd.ftz r3 r2 [sub, sub, subr, subr]
r3  = fadd.ftz -rZ |r3|
r16 = shfl.bfly r2 0x1 0x1c03
r16 = fswzadd.ftz r16 r2 [sub, subr, sub, subr]
r16 = fadd.ftz -rZ |r16|
r3  = fadd.ftz r16 r3

into:

r3  = shfl.bfly r2 0x2 0x1c03
r3  = fswzadd.ftz r3 r2 [sub, sub, subr, subr]
r16 = shfl.bfly r2 0x1 0x1c03
r16 = fswzadd.ftz r16 r2 [sub, subr, sub, subr]
r3  = fadd.ftz |r16| |r3|

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12480
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33107>
2025-04-17 02:22:02 +00:00
Faith Ekstrand
47fc468944 nak/sm70: Fix the bit74_75_ar_mod assert
It's used for src2, not src0.

Fixes: 40422927dc ("nak: Pass has_mod to all form of src2 requiring it")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33107>
2025-04-17 02:22:02 +00:00
Faith Ekstrand
328112c6bc nak/legalize: Take a RegFile in copy_alu_src_and_lower_ineg()
Fixes: af6093a712 ("nak/legalize: Add a helper for lowering ineg")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33107>
2025-04-17 02:22:02 +00:00
Faith Ekstrand
22a30bfa4f nak/legalize: Take a RegFile in copy_alu_src_and_lower_fmod
Otherwise, we'll screw up uniform GPRs.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33107>
2025-04-17 02:22:02 +00:00
Caio Oliveira
d5ad798140 spirv, radv, intel: Add NIR intrinsic for cmat conversion
A cooperative matrix conversion operation was represented in NIR by the
cmat_unary_op intrinsic with an nir_alu_op as extra parameter,
that was already lowered to a specific conversion operation
based on the matrix types.

Instead of that, add a new intrinsic `cmat_convert` that is specific
for that conversion.  In addition to the src/dst matrix descriptions
already available, also include the signedness information in the
intrinsic (reuse nir_cmat_signed for that).  This is needed because
different Convert operations define different interpretations for
integers, regardless their original type.

In this patch, both radv and intel were changed to use the same logic
that was previously used to pick the lowered ALU op.

This change will help represent cmat conversions involving BFloat16,
because it avoids having to create new NIR ALU ops for all the
combinations involving BFloat16.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34511>
2025-04-16 23:13:36 +00:00
Valentine Burley
2f02fa5db4 intel/ci: Start using the new 6.14 kernel on JSL
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The new 6.14 kernel in gfx-ci linux is now stable on Jasper Lake, so drop
the kernel override from the anv-jsl-vk job.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34553>
2025-04-16 22:13:19 +00:00
Patrick Lerda
60a31156b0 mesa_interface: fix legacy dri2 compatibility
These values are shared with xcb/dri2.h, and can't be changed
without breaking the legacy dri2 compatibility. This change
reverses partially the update done by 3b603d1646.

For instance this issue is triggered on dri2 i915 with
"piglit/bin/glx-copy-sub-buffer -auto" or
"piglit/bin/hiz-depth-read-window-stencil0 -auto".

Fixes: 3b603d1646 ("mesa_interface: remove unused stuff")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34561>
2025-04-16 20:19:14 +00:00
Mike Blumenkrantz
de6efc01c1 zink: verify that surface exists when adding implicit feedback loop
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
this can be null if multiple contexts are in use

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34557>
2025-04-16 18:26:32 +00:00