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radv: simplify combining TES/VS+GS config registers

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34518>
This commit is contained in:
Samuel Pitoiset 2025-04-14 11:23:36 +02:00 • committed by Marge Bot
parent 0dd9833348
commit 85fdf69027
3 changed files with 26 additions and 42 deletions
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40
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2271,18 +2271,11 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer)
radeon_set_sh_reg(vs->info.regs.pgm_rsrc1, rsrc1);
} else {
radv_shader_combine_cfg_vs_gs(vs, next_stage, &rsrc1, &rsrc2);
unsigned lds_size;
if (next_stage->info.is_ngg) {
lds_size = DIV_ROUND_UP(next_stage->info.ngg_info.lds_size, pdev->info.lds_encode_granularity);
} else {
lds_size = next_stage->info.gs_ring_info.lds_size;
}
radv_shader_combine_cfg_vs_gs(device, vs, next_stage, &rsrc1, &rsrc2);
radeon_set_sh_reg_seq(vs->info.regs.pgm_rsrc1, 2);
radeon_emit(rsrc1);
radeon_emit(rsrc2 | S_00B22C_LDS_SIZE(lds_size));
radeon_emit(rsrc2);
}
radeon_end();
@ -2333,21 +2326,14 @@ radv_emit_tess_eval_shader(struct radv_cmd_buffer *cmd_buffer)
const struct radv_shader *gs = cmd_buffer->state.shaders[MESA_SHADER_GEOMETRY];
uint32_t rsrc1, rsrc2;
radv_shader_combine_cfg_tes_gs(tes, gs, &rsrc1, &rsrc2);
unsigned lds_size;
if (gs->info.is_ngg) {
lds_size = DIV_ROUND_UP(gs->info.ngg_info.lds_size, pdev->info.lds_encode_granularity);
} else {
lds_size = gs->info.gs_ring_info.lds_size;
}
radv_shader_combine_cfg_tes_gs(device, tes, gs, &rsrc1, &rsrc2);
radeon_begin(cmd_buffer->cs);
radeon_set_sh_reg(tes->info.regs.pgm_lo, tes->va >> 8);
radeon_set_sh_reg_seq(tes->info.regs.pgm_rsrc1, 2);
radeon_emit(rsrc1);
radeon_emit(rsrc2 | S_00B22C_LDS_SIZE(lds_size));
radeon_emit(rsrc2);
const uint32_t next_stage_pc_offset = radv_get_user_sgpr_loc(tes, AC_UD_NEXT_STAGE_PC);
radeon_emit_32bit_pointer(next_stage_pc_offset, gs->va, &pdev->info);
@ -5109,7 +5095,8 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
if (vs_shader->info.merged_shader_compiled_separately) {
if (vs_shader->info.next_stage == MESA_SHADER_GEOMETRY) {
radv_shader_combine_cfg_vs_gs(vs_shader, cmd_buffer->state.shaders[MESA_SHADER_GEOMETRY], &rsrc1, &rsrc2);
radv_shader_combine_cfg_vs_gs(device, vs_shader, cmd_buffer->state.shaders[MESA_SHADER_GEOMETRY], &rsrc1,
&rsrc2);
} else {
assert(vs_shader->info.next_stage == MESA_SHADER_TESS_CTRL);
@ -5131,20 +5118,7 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
radeon_set_sh_reg(vs_shader->info.regs.pgm_rsrc1, rsrc1);
if (vs_shader->info.merged_shader_compiled_separately) {
if (vs_shader->info.next_stage == MESA_SHADER_GEOMETRY) {
const struct radv_shader *gs = cmd_buffer->state.shaders[MESA_SHADER_GEOMETRY];
unsigned lds_size;
if (gs->info.is_ngg) {
lds_size = DIV_ROUND_UP(gs->info.ngg_info.lds_size, pdev->info.lds_encode_granularity);
} else {
lds_size = gs->info.gs_ring_info.lds_size;
}
radeon_set_sh_reg(vs_shader->info.regs.pgm_rsrc2, rsrc2 | S_00B22C_LDS_SIZE(lds_size));
} else {
radeon_set_sh_reg(vs_shader->info.regs.pgm_rsrc2, rsrc2);
}
radeon_set_sh_reg(vs_shader->info.regs.pgm_rsrc2, rsrc2);
}
radeon_end();

20
src/amd/vulkan/radv_shader.c
View file

@ -2296,9 +2296,11 @@ radv_shader_combine_cfg_vs_tcs(const struct radv_shader *vs, const struct radv_s
}
void
radv_shader_combine_cfg_vs_gs(const struct radv_shader *vs, const struct radv_shader *gs, uint32_t *rsrc1_out,
uint32_t *rsrc2_out)
radv_shader_combine_cfg_vs_gs(const struct radv_device *device, const struct radv_shader *vs,
const struct radv_shader *gs, uint32_t *rsrc1_out, uint32_t *rsrc2_out)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
assert(G_00B12C_USER_SGPR(vs->config.rsrc2) == G_00B12C_USER_SGPR(gs->config.rsrc2));
if (rsrc1_out) {
@ -2316,22 +2318,30 @@ radv_shader_combine_cfg_vs_gs(const struct radv_shader *vs, const struct radv_sh
if (rsrc2_out) {
uint32_t rsrc2 = vs->config.rsrc2;
uint32_t lds_size;
if (G_00B22C_ES_VGPR_COMP_CNT(gs->config.rsrc2) > G_00B22C_ES_VGPR_COMP_CNT(rsrc2))
rsrc2 = (rsrc2 & C_00B22C_ES_VGPR_COMP_CNT) | (gs->config.rsrc2 & ~C_00B22C_ES_VGPR_COMP_CNT);
rsrc2 |= gs->config.rsrc2 & ~(C_00B12C_SCRATCH_EN & C_00B12C_SO_EN & C_00B12C_SO_BASE0_EN & C_00B12C_SO_BASE1_EN &
C_00B12C_SO_BASE2_EN & C_00B12C_SO_BASE3_EN);
if (gs->info.is_ngg) {
lds_size = DIV_ROUND_UP(gs->info.ngg_info.lds_size, pdev->info.lds_encode_granularity);
} else {
lds_size = gs->info.gs_ring_info.lds_size;
}
rsrc2 |= S_00B22C_LDS_SIZE(lds_size);
*rsrc2_out = rsrc2;
}
}
void
radv_shader_combine_cfg_tes_gs(const struct radv_shader *tes, const struct radv_shader *gs, uint32_t *rsrc1_out,
uint32_t *rsrc2_out)
radv_shader_combine_cfg_tes_gs(const struct radv_device *device, const struct radv_shader *tes,
const struct radv_shader *gs, uint32_t *rsrc1_out, uint32_t *rsrc2_out)
{
radv_shader_combine_cfg_vs_gs(tes, gs, rsrc1_out, rsrc2_out);
radv_shader_combine_cfg_vs_gs(device, tes, gs, rsrc1_out, rsrc2_out);
if (rsrc2_out) {
*rsrc2_out |= S_00B22C_OC_LDS_EN(1);

8
src/amd/vulkan/radv_shader.h
View file

@ -724,11 +724,11 @@ enum radv_pipeline_type;
void radv_shader_combine_cfg_vs_tcs(const struct radv_shader *vs, const struct radv_shader *tcs, uint32_t *rsrc1_out,
uint32_t *rsrc2_out);
void radv_shader_combine_cfg_vs_gs(const struct radv_shader *vs, const struct radv_shader *gs, uint32_t *rsrc1_out,
uint32_t *rsrc2_out);
void radv_shader_combine_cfg_vs_gs(const struct radv_device *device, const struct radv_shader *vs,
const struct radv_shader *gs, uint32_t *rsrc1_out, uint32_t *rsrc2_out);
void radv_shader_combine_cfg_tes_gs(const struct radv_shader *tes, const struct radv_shader *gs, uint32_t *rsrc1_out,
uint32_t *rsrc2_out);
void radv_shader_combine_cfg_tes_gs(const struct radv_device *device, const struct radv_shader *tes,
const struct radv_shader *gs, uint32_t *rsrc1_out, uint32_t *rsrc2_out);
const struct radv_userdata_info *radv_get_user_sgpr_info(const struct radv_shader *shader, int idx);