Commit graph

13610 commits

Author SHA1 Message Date
Samuel Pitoiset
47f666b64b radv: enable extendedDynamicState3AlphaToCoverageEnable on GFX11
This is now supported and this allows Zink to enable full ds3 mode for
even less stuttering. DXVK also uses dynamic alpha to coverage
sometimes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26250>
2023-12-06 16:36:16 +00:00
Samuel Pitoiset
bca4ebc3c4 radv: export MRTZ via PS epilogs when alpha to coverage is dynamic on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26250>
2023-12-06 16:36:16 +00:00
Samuel Pitoiset
79cf2b6824 radv: determine and emit SPI_SHADER_Z_FORMAT for PS epilogs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
4248d0b03a radv,aco: declare PS epilog VGPR arguments for depth/stencil/samplemask
Depth/stencil/samplemask inputs are first to match
create_fs_jump_to_epilog().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
8b87c985b0 radv: prepare the PS epilog key for exporting MRTZ on RDNA3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
5b01285cfb radv: determine if MRTZ needs to be exported via PS epilogs
For GFX11 only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
b2a37b4304 ac/nir: add an option to skip MRTZ exports in ac_nir_lower_ps()
On RDNA3, alpha to coverage needs to be exported through MRTZ when
depth, stencil or samplemask are also exported. This option will allow
us to export MRTZ from PS epilogs instead of the main FS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
81eeb157f8 aco: export depth/stencil/samplemask in create_fs_jump_to_epilog()
This currently has no effects because the store_output instructions
are removed earlier (in ac_nir_lower_ps). Though, this will be needed
for exporting MRTZ from PS epilogs for alpha to coverage on RDNA3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Eric Engestrom
90a77f55de ci: drop containers, builds, and tests from post-merge pipeline
All these jobs are redundant and a waste of resources:
- the containers have already been built & pushed in the merge pipeline
- the mesa build variants have already all passed
- the driver tests have already all passed

None of these jobs are doing anything useful in this pipeline, but it
costs a factor of 2x to our infrastructure, so let's remove them.

In other words, the only job left in the post-merge pipeline is the
`pages` job that deploys the update to the website.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26451>
2023-12-06 08:26:04 +00:00
Samuel Pitoiset
a3b3a7d36a radv: remove unused code for compiling PS epilogs as part of pipelines
Since we switched to the "on-demand" path for GPL, this is dead code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
2023-12-06 08:01:46 +00:00
Samuel Pitoiset
725fc0ec03 radv: switch to on-demand PS epilogs for GPL
RADV currently has two paths for PS epilogs:
- the first one is mostly used by GPL to compile fragment shader epilogs
  as part of the graphics pipeline. It's supposed to be optimal because
  fragment shader epilogs are compiled in the pipeline and eventually
  cached.
- the second one (the "on-demand" path) is required when some dynamic
  states are used because otherwise it's just impossible to compile the
  fragment shader. These epilogs are compiled during cmdbuf recording
  when all needed info are known, they are also cached in memory. This
  is the main path for Zink.

Having two different paths isn't ideal for maintenance but there is
another problem. On RDNA3, alpha to coverage needs to be exported as
part of MRTZ when either depth/stencil/samplemask are exported. The
problem being that with GPL, the PSO multisample state can be NULL when
the frag shader lib is created, which means that we can't know if atc
needs to be exported or not, even if it's static. The solution seems to
to always use on-demand fragment shader epilogs for GPL on RDNA3.

So far, I think that switching to on-demand PS epilogs unconditionally
for GPL shouldn't hurt performance and that will simplify a lot of
things.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
2023-12-06 08:01:45 +00:00
Qiang Yu
7656251294 aco: fix set_wqm segfault when ps prolog
ps prolog does not have nir shader.

Fixes: 3b10547e67 ("aco: enable helper lanes if shader->info.fs.require_full_quads")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26512>
2023-12-06 05:34:30 +00:00
Eric Engestrom
df8ea977be radeonsi/ci: track changes to vpelib
According to `src/amd/meson.build`, radeonsi uses vpelib, so we should
track changes to it as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26479>
2023-12-06 01:58:41 +00:00
Samuel Pitoiset
3678482f1e radv: set combinedImageSamplerDescriptorCount to 1 for multi-planar formats
RADV compacts all descriptors for multi-planar images into one
combined image sampler, so it should be 96, and not eg. 192 for a two
planes format.

Fixes new CTS
dEQP-VK.binding_model.descriptor_buffer.ycbcr_sampler.*array.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26498>
2023-12-05 22:27:19 +00:00
Rhys Perry
e110eac171 aco: insert p_end_wqm before p_jump_to_epilog
Otherwise, we can transition to exact before p_jump_to_epilog, then
transition to WQM again and then back to exact:
p_jump_to_epilog //transitions to exact
p_logical_end //transitions to wqm
p_end_wqm //transitions to exact

We rely on ssa elimination to clean most of this up.

fossil-db (navi21):
Totals from 1 (0.00% of 79330) affected shaders:
Instrs: 111 -> 110 (-0.90%)
CodeSize: 572 -> 568 (-0.70%)
Copies: 16 -> 15 (-6.25%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25440>
2023-12-05 21:02:04 +00:00
Samuel Pitoiset
13dcbdcdf3 radv: make sure to reset the stipple line state when it's disabled
In a scenario like:
CmdBindPipeline(stipple line enabled)
CmdDraw()
CmdBindPipeline(stipple line disabled)
CmdDraw()

The second draw wasn't resetting the stipple line state and this might
have caused issues, though it's uncovered by VK CTS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26429>
2023-12-05 18:29:30 +00:00
Samuel Pitoiset
e88973fd02 radv: change the reset stipple pattern mode for adjacent lines
Ported from RadeonSI. This isn't covered by VK CTS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26429>
2023-12-05 18:29:29 +00:00
Samuel Pitoiset
16d5ffc3ee radv: update the reset stipple pattern mode
PAL recently changed the mode. This doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26429>
2023-12-05 18:29:29 +00:00
Samuel Pitoiset
949fdc9a73 radv: advertise VK_EXT_depth_clamp_zero_one
RADV already implements this behavior, so enabling this extension is
a no-op.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26443>
2023-12-05 18:10:31 +00:00
Rhys Perry
7a37a39fe0 aco: simplify v_mul_* labelling slightly
This was from before VALU_instruction existed.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
2023-12-05 16:56:58 +00:00
Rhys Perry
468ee8b80c aco: implement 16-bit fsat on GFX8
GFX8 doesn't have v_med3_f16.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
2023-12-05 16:56:58 +00:00
Rhys Perry
de51a21e26 aco: implement 16-bit derivatives
These are used by radeonsi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
2023-12-05 16:56:58 +00:00
Rhys Perry
997a0884a5 aco: implement 16-bit fsign on GFX8
GFX8 doesn't have v_med3_i16.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
2023-12-05 16:56:58 +00:00
Rhys Perry
b7725b072b aco: flush denormals for 16-bit fmin/fmax on GFX8
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26445>
2023-12-05 16:56:57 +00:00
Samuel Pitoiset
338319741c radv: add DGC support for mesh shader only
This only implements mesh shaders with DGC because task shaders are
really tricky. I will address them later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
2023-12-05 14:17:39 +00:00
Samuel Pitoiset
eb3e1bdfe6 radv: only initialize the VTX base SGPR if non-zero with DGC
Otherwise, its value is incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
2023-12-05 14:17:39 +00:00
Samuel Pitoiset
1deedc70db radv: only initialize the VBO reg if VBOs are bound with DGC
With mesh shader there is no VBO at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
2023-12-05 14:17:39 +00:00
Samuel Pitoiset
400cfa0eba radv: remove never used binds_state for DGC
This has been removed a while ago.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
2023-12-05 14:17:39 +00:00
Eric Engestrom
48324e3734 radeonsi/ci: update vangogh piglit expectations
Looking good there, Vangogh!

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26466>
2023-12-05 13:34:32 +00:00
Martin Roukala (né Peres)
91076fd390 amd/ci: reduce Renoir's concurrency to 16
It seems like when we increased the number of tests per shard, we
started overcommitting the Renoir runner, leading to load averages
higher than the 16 CPU threads could handle, while also running at
75-96% memory usage.

By dropping the concurrency to 16, we should be able to reduce this
memory usage while also reducing the execution time.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26501>
2023-12-05 12:45:44 +00:00
Yonggang Luo
83a5fb9faf util: Fixes note: the alignment of ‘_Atomic long long int’ fields changed in GCC 11.
This is a improve of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22121

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23961>
2023-12-05 09:26:08 +00:00
Eric Engestrom
3115e6e211 amd/ci: reuse .radeonsi-rules in .radeonsi-vaapi-rules
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26480>
2023-12-05 06:55:21 +00:00
Eric Engestrom
ebaede788e amd/ci: limit radv jobs to radv + aco files changes
Otherwise, any change in src/amd/ would always trigger all the radv
jobs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26460>
2023-12-04 20:43:53 +00:00
Eric Engestrom
03d8ea9912 amd/ci: split common amd files list from radeonsi files list
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26460>
2023-12-04 20:43:53 +00:00
Eric Engestrom
98f0800c94 amd/ci: fix yaml indentation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26460>
2023-12-04 20:43:53 +00:00
Friedrich Vock
d6d68ceda1 radv: Enable compute dispatch tunneling
Compute tunneling can considerably lower the latency of high-priority
compute work. Enabling it is beneficial in cases where high-priority
work is dispatched while the GPU is already busy with other work (e.g.
rendering on GFX). This is the case in VR compositors that dispatch
latency-sensitive compositing work to ACE while GFX is busy rendering
the next frame.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26462>
2023-12-04 12:32:47 +00:00
Eric Engestrom
778000ec7f radv: update symbols that have become aliases for newer ones
All of these have been renamed in the spec (usually by being promoted);
renamed them in our code too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26490>
2023-12-04 10:45:48 +00:00
Felix bridault
059391b631 radv: use 32bit va range for sparse descriptor buffers
Fixes: 5c5735fd68 ("radv: advertise VK_EXT_descriptor_buffer")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26482>
2023-12-04 09:59:29 +00:00
Samuel Pitoiset
9027c6d8ca radv: adjust assertions for multi-layer resolves with the HW/FS paths
Only compute supports layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
70556739e0 radv: only re-initialize DCC for one level for the HW resolve path
The source image can only have one level, so only level in the
destination image needs to be re-initialized.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
91aaf0c663 radv: remove unused layers support for the HW/FS resolve paths
The driver always fallbacks to the compute resolve path when either
the source or destination images have layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
aae2595390 radv: stop performing redundant resolves with the HW resolve path
This path was quadratic...
Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Samuel Pitoiset
e425f92f3e radv: simplify creating image views for src resolve images
The Vulkan spec says:

"If samples is not VK_SAMPLE_COUNT_1_BIT, then imageType must be
 VK_IMAGE_TYPE_2D, flags must not contain
 VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT, mipLevels must be equal to 1..."

So, the source image is always 2D with no mipmaps.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26316>
2023-12-04 08:12:16 +00:00
Eric Engestrom
2cdebf51fd amd/ci: radeonsi is gl, not vk
Fixes: cf323446e7 ("amd/ci: run gl(es) cts & piglit on radeonsi on vangogh")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26478>
2023-12-03 13:57:38 +00:00
Eric Engestrom
402210034b radv/ci: add navi21-aco flake
Failed once in https://gitlab.freedesktop.org/mesa/mesa/-/jobs/52219125
but passed in the automatic retry.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26467>
2023-12-02 09:33:46 +00:00
Samuel Pitoiset
bd54592487 radv: remove radv_pipeline_key::dynamic_color_write_mask
When this state is dynamic, the common runtime code sets the write mask
to 0xf which prevents color exports to be removed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26400>
2023-12-01 15:50:04 +00:00
Martin Roukala (né Peres)
a6f22aa182 radv: disable meshShaderQueries on gfx10.3
They have been causing hangs intermitently in CI for the past week,
until it finally caught my attention and forced me spend a couple of
hours bisecting the issue.

We'll re-introduce support for it when the issue is fixed.

Fixes: b975d4e800 ("radv: enable meshShaderQueries on GFX10.3")
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26450>
2023-12-01 15:17:48 +00:00
Samuel Pitoiset
ced313eec8 radv: make sure to prefetch the compute shader for DGC
It was never prefetched. These two helpers should be refactored with
radv_dispatch() though.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
2023-12-01 12:25:46 +00:00
Samuel Pitoiset
ab6cf1592f radv: fix bogus interaction between DGC and RT with descriptor bindings
pipeline_is_dirty was never TRUE because it's emitted in the before
helper. This might fix bad interactions between DGC and RT because
they both use compute shaders and descriptor bindings need to be
re-emitted.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
2023-12-01 12:25:46 +00:00
Tatsuyuki Ishi
eb0419a1aa radv: Remove aspect mask "expansion" for copy_image.
The Vulkan spec says multi-planar images can only be copied on a
per-plane basis. The COLOR_BIT to "all planes" expansion applies to
image memory barriers which is completely unrelated.

Remove the expansion logic to simplify the code. Add assertions to
clearly describe the invariant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26364>
2023-12-01 01:52:04 +00:00