Commit graph

13547 commits

Author SHA1 Message Date
Daniel Schürmann
c298ab0d23 aco: correctly validate v_fma_mixhi_f16 register assignment
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
2022-06-27 15:07:27 +00:00
Samuel Pitoiset
fd997bde2f radv: dump UMR waves before UMR rings
Dumping UMR rings might be slow and dumping waves before would make it
more chance to dump them without reporting "No active waves".

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
2022-06-27 08:36:49 +00:00
Samuel Pitoiset
4c908d4587 radv: fix command line for dumping waves with UMR
GFXOFF must be disabled before dumping waves and re-enabled after.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
2022-06-27 08:36:49 +00:00
Samuel Pitoiset
915bc6a179 radv: use RADEON_FLAG_VA_UNCACHED for the trace BO
Figured this while debugging a GPU hang with a simple CTS test. This
is to make sure data written by the CP are coherent on the CPU.

This also explains spurious GPU hang reports generated for Hitman 3
that made no sense without it. Now it's clear that this game hangs
after a DRAW_INDEX_INDIRECT packet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
2022-06-27 08:36:49 +00:00
Samuel Pitoiset
db7890637e radv: disable small primitive culling for user sample locations
The driver can't assume sample positions at (0.5, 0.5) when user
sample locations are used.

This doesn't fix anything in practice because NGGC is only enabled by
default on GFX10.3 and that extension is currently disabled on GFX10+,
but I would like to expose it at some point.

This fixes dEQP-VK.pipeline.*.sample_locations_ext.verify_location.*
(when the extension is enabled locally).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17228>
2022-06-27 08:10:08 +00:00
Qiang Yu
04b15f88e7 radeonsi: replace llvm gs input handle with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:50 +08:00
Qiang Yu
36197b8dc0 ac/llvm: get back nir_intrinsic_load_gs_vertex_offset_amd
Will be used by radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:46 +08:00
Qiang Yu
e9f1f115fa ac/nir: add triangle_strip_adjacency_fix to gs input lower
From radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:43 +08:00
Qiang Yu
109eb378e5 ac/nir: change es output lower param to esgs_itemsize
radeonsi may add extra dword to the stride, so let's pass it
directly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:34 +08:00
Qiang Yu
8b5e8b2af7 ac/nir: remove unused param num_reserved_es_outputs from gs input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:30 +08:00
Qiang Yu
7ddd15f6c7 ac/nir: skip gl_ViewportIndex and gl_Layer write in ES
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:21 +08:00
Qiang Yu
06d493dde2 radeonsi: implement two esgs ring nir intrinsic
nir_intrinsic_load_ring_esgs_amd
nir_intrinsic_load_ring_es2gs_offset_amd

Will be used by esgs lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:15 +08:00
Qiang Yu
9fc01f6e79 ac/llvm: fix code format alignment in visit_load_local_invocation_index
Used tab instead of space.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:00 +08:00
Qiang Yu
7847114343 radeonsi: replace llvm tes input load with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
2b7e167bbd radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
This can remove special handling of tessfactors which also benifit
the nir lower pass which does not handle these as system value.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
7598bfd768 radeonsi: replace llvm tcs output with nir lower pass
Remove the store_tcs_outputs abi, we can use common output abi
to handle the tessfactor pass as vgpr.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
d00845faf4 ac/nir: add no_input_lds_space param to hs output lower
This is used by radeonsi to save some lds space when all LS output
is passed by register.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
8f8d06bd05 ac/llvm: handle write mask for nir_intrinsic_store_buffer_amd
tess lowering may generate buffer store with partial write mask.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
baaeca7d1a radeonsi: implement nir_intrinsic_load_tess_rel_patch_id_amd for both tcs and tes
radv will lower this intrinsic before gets to llvm, so we just need to
implement it in radeonsi.

The tes version will be used in tess lower too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
3853dfcd44 radeonsi: implement nir_intrinsic_load_ring_tess_offchip(_offset)_amd
Used by tess lower latter.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
ae9b02b4d0 ac/nir: add wave_size parameter to ac_nir_lower_hs_outputs_to_mem
Used by radeonsi and radv to reflect true wave size used, not minimal size.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
18d51831a8 ac/nir: add pass_tessfactors_by_reg param to hs output lower
radeonsi won't emit tess factor in the lower pass, need to keep
the output for llvm backend to pass it as parameter. This is used
by radeonsi for an optimization to save LDS write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
6ccb9634de ac/nir: use nir_intrinsic_load_hs_out_patch_data_offset_amd in tess lower
radeonsi load this from SGPR arg, can't use static value because TCS output
and TES input may not match (TCS output is not a key for TES) and
determined in runtime.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
fdf589321c ac/nir: add nir_intrinsic_load_hs_out_patch_data_offset_amd
Also add radv and radeonsi implementation. Will be used in tess lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
2ba6d2b107 ac/nir: remove unused parameter in tes input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
07e025a390 radeonsi: implement nir_intrinsic_load_tcs_num_patches_amd
Used by ac_nir_lower_tess_io_to_mem.c.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu
3aa70d92ce radv: no need to do gs_alloc_req for newer chips in ngg vs/tes
Copy from radeonsi.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
2022-06-27 02:12:13 +00:00
Qiang Yu
74e596a5f0 ac/llvm: conditionally check wave id in gs sendmsg
nir lowering already call this with wave id check, no need to
check inside ac_build_sendmsg_gs_alloc_req again.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
2022-06-27 02:12:13 +00:00
Bas Nieuwenhuizen
e75f11625d radv: Deal with derefs from opaque types in function parameters.
Needs more copy propagation before nir_opt_derefs picks it up.

Note that the full general problem of opaque types stored in
intermediate variables is still open, but that seems like a whole
can of worms, and no sense to have gfxbench stay broken during the
time it takes to solve that.

Cc: mesa-stable
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5945
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17012>
2022-06-27 01:23:43 +00:00
Rhys Perry
33641b2a26 aco: cleanup force-waitcnt output
If we don't reset ctx.vm_cnt/gpr_map/etc, this will spam a lot of
s_waitcnt instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17207>
2022-06-24 12:44:55 +00:00
Georg Lehmann
ed429af586 radv: Don't check if we need to copy immutable samplers for non push templates.
This should allow the compiler to optimize this out because it knows that
cmd_buffer is NULL.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17166>
2022-06-24 06:32:43 +00:00
Andres Gomez
01a1af1819 radv/ci: update vkd3d-proton results for AMD's Kabini
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
2022-06-24 05:32:53 +00:00
Rhys Perry
6fc2622abd aco: don't skip VS->TCS barrier if TCS output vertices doesn't match input
TCS invocations correspond to output patch vertices, not input. If they
differ, TCS invocations can be in a different subgroup than VS invocations
of the input patch.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6564
Fixes: 152092b8ea ("aco: skip s_barrier if TCS patches are within subgroup")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17174>
2022-06-23 10:08:02 +00:00
Samuel Pitoiset
ad3d6d9c6e radv/llvm: always emit a null export even if the FS doesn't discard
Even with a noop FS, the color blend state can still be non-zero, and
then SPI color related registers won't be 0 and this would hang.

Fixes: bdf3797aeb ("ac,radeonsi: don't export null from PS if it has no effect on gfx10+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17169>
2022-06-22 08:31:30 +02:00
Martin Roukala (né Peres)
677a42378b ci/radv: add a missing flake
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
2022-06-21 13:11:05 +03:00
Martin Roukala (né Peres)
f86e12743c ci/radv: move a test from the fail list to the flake list
The test was misidentified as a "fail", when it actually has a very
high failure rate (>95%). The test happened to pass twice within the
last week, so let's mark this test as a flake.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
2022-06-21 13:10:51 +03:00
Samuel Pitoiset
6cab999d6a radv,aco: rename radv_prolog_binary/radv_shader_prolog to shader_part
The same structures and functions will be re-used for PS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17084>
2022-06-21 08:04:50 +00:00
Vinson Lee
2b87073133 radv: Remove unnecessary null check.
Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking subpass suggests that it may be null,
but it has already been dereferenced on all paths leading to the check.

Fixes: 779e09639b ("radv: configure DB_Z_INFO.NUM_SAMPLES correctly on GFX11")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17100>
2022-06-21 04:00:46 +00:00
Georg Lehmann
7afecd8ad8 radv: Check descriptor pool entry count before allocating a new set.
It's simpler and more efficient.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17127>
2022-06-20 10:50:01 +00:00
Georg Lehmann
ceb3ae2afb radv: Remove redundant memset in radv_descriptor_set_create.
The memset below also clears this memory, plus the descriptor set header.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17127>
2022-06-20 10:50:01 +00:00
Samuel Pitoiset
5485bf7b1b aco: fix validation of SOP1 instructions without definitions
Like s_setpc_b64.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17082>
2022-06-20 07:08:28 +00:00
Samuel Pitoiset
6dd2699e9f radv/amdgpu: do not add "global" BO to the virtual BO list
To avoid dangling BO references if it's destroyed without being
previously unbound. This is under Vulkan spec clarification but it
looks like the "global" BO fix is simple enough to workaround the
issue for now.

This fixes a CPU hang with Halo Infinite because the kernel rejects
a submission (invalid BO handle found).

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17085>
2022-06-20 06:43:53 +00:00
Samuel Pitoiset
b4cc10b342 radv/amdgpu: make sure to reset the number of BO when there is no ranges
If an application binds a sparse resource and then unbind it with NULL,
the number of "real" BOs in the virtual BO list should be reset to 0.
Otherwise, it might use a dangling BO reference if it's destroyed just
after being unbound.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17085>
2022-06-20 06:43:53 +00:00
Martin Roukala (né Peres)
8a9f7087a1 radv/ci: test vkd3d on kabini
The machine is extremely slow and fails to finish vkcts, but vkd3d may
still be used as a way to detect extreme regressions.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17081>
2022-06-18 19:33:24 +03:00
Samuel Pitoiset
16c47ad347 radv: advertise VK_EXT_border_color_swizzle on GFX10+
On GFX9 and older, the driver needs to swizzle itself it seems.
Exposing it on GFX10+, allows us to test it with Zink, at least.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17057>
2022-06-16 18:31:33 +00:00
Samuel Pitoiset
9df7ad0320 radv/ci: add vkd3d-proton testing
The vkd3d-proton can be very useful, I recently found issues while
implementing VK_EXT_primitives_generated_query and
VK_KHR_fragment_shader_barycentric.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17050>
2022-06-16 06:36:36 +00:00
Samuel Pitoiset
3f2de5e662 radv/ci: refactor test machines and dEQP rules to reduce copy&paste config
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17050>
2022-06-16 06:36:36 +00:00
Ruijing Dong
515112eabd radeonsi/vcn: prepare for unified queue in vcn4
- apply unified queue ib headers to vcn4
  - re-use encoding queue as unified queue
  - define unified queue functions and structures

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16911>
2022-06-16 03:30:47 +00:00
Rhys Perry
33e7ba2e3e aco: update SMEM offset workaround for LLVM 15
This isn't needed since LLVM 15's b0ccf38b018.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6663
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17036>
2022-06-16 00:47:51 +00:00
Marek Olšák
ee7150da79 amd/gfx11: add PixelWaitSync packet fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16990>
2022-06-15 20:52:42 +00:00