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ac/nir: add wave_size parameter to ac_nir_lower_hs_outputs_to_mem

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Used by radeonsi and radv to reflect true wave size used, not minimal size.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
This commit is contained in:
Qiang Yu 2022-05-27 17:39:18 +08:00 • committed by Marge Bot
parent 18d51831a8
commit ae9b02b4d0
3 changed files with 4 additions and 2 deletions
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1
src/amd/common/ac_nir.h
View file

@ -89,6 +89,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
uint64_t tes_patch_inputs_read,
unsigned num_reserved_tcs_outputs,
unsigned num_reserved_tcs_patch_outputs,
unsigned wave_size,
bool pass_tessfactors_by_reg,
bool emit_tess_factor_write);

3
src/amd/common/ac_nir_lower_tess_io_to_mem.c
View file

@ -705,6 +705,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
uint64_t tes_patch_inputs_read,
unsigned num_reserved_tcs_outputs,
unsigned num_reserved_tcs_patch_outputs,
unsigned wave_size,
bool pass_tessfactors_by_reg,
bool emit_tess_factor_write)
{
@ -717,7 +718,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
.tes_patch_inputs_read = tes_patch_inputs_read,
.tcs_num_reserved_outputs = num_reserved_tcs_outputs,
.tcs_num_reserved_patch_outputs = num_reserved_tcs_patch_outputs,
.tcs_out_patch_fits_subgroup = 32 % shader->info.tess.tcs_vertices_out == 0,
.tcs_out_patch_fits_subgroup = wave_size % shader->info.tess.tcs_vertices_out == 0,
.tcs_pass_tessfactors_by_reg = pass_tessfactors_by_reg,
.map_io = map,
};

2
src/amd/vulkan/radv_shader.c
View file

@ -1124,7 +1124,7 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta
device->physical_device->rad_info.gfx_level,
info->tcs.tes_reads_tess_factors, info->tcs.tes_inputs_read,
info->tcs.tes_patch_inputs_read, info->tcs.num_linked_outputs,
info->tcs.num_linked_patch_outputs, false, true);
info->tcs.num_linked_patch_outputs, info->wave_size, false, true);
return true;
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {