Commit graph

13547 commits

Author SHA1 Message Date
Qiang Yu
13fb7f8f2c ac/nir/ngg,ac/llvm,aco: save nogs ngg culling one lds dword
TES rel patch id is <256, so we can use an existing unused LDS
byte instead of extra dword.

To ease the programing, change the index of repacked_arg_vars
for these variables.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
2022-10-27 07:35:01 +00:00
Qiang Yu
66d1fa9666 ac/nir/ngg: save and restore no_varying/no_sysval_output
These are used by radeonsi for param export count, should
be saved and restore.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
2022-10-27 07:35:01 +00:00
Qiang Yu
b197dd0d15 ac/nir/ngg: allow passthrough with vs primitive id output
vertex primtive id and passthrough are not exclusive, just need
to get correct vertex index when passthrough.

radeonsi won't disable passthrough when vs primitive id output,
this is also for fixing the crash of the assertion.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
2022-10-27 07:35:01 +00:00
Qiang Yu
e536d0fe4b ac/nir/ngg,radv: move LDS layout calculation out of nir ngg lowering
Use lds base load intrinsics in nir ngg lowering to get layout, left
its calulation to driver.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
2022-10-27 07:35:01 +00:00
Qiang Yu
54eea0e393 ac/nir/ngg: pass primitive_id_location as param for nogs lower
radeonsi need to use packed driver location for all outputs,
while radv need to use VARYING_SLOT_*. To meet both drivers'
needs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
2022-10-27 07:35:01 +00:00
Qiang Yu
d82b668bc6 ac/nir/ngg: support user edge flags for ngg lower
Pack user edge flag into arg code is ported from radeonsi
gfx10_ngg_build_export_prim.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
2022-10-27 07:35:01 +00:00
Qiang Yu
238eeeacb2 ac/llvm: get back intrinsics used by NGG
Will be used by radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
2022-10-27 07:35:01 +00:00
Lionel Landwerlin
53a0804146 radv: tweak lower_shader_calls parameters
On Q2RTX shaders :

MaxWaves: 62 -> 69 (+11.29%)
Instrs: 41626 -> 41575 (-0.12%); split: -0.27%, +0.15%
CodeSize: 224960 -> 223740 (-0.54%); split: -0.62%, +0.08%
VGPRs: 800 -> 704 (-12.00%)
Scratch: 75776 -> 70656 (-6.76%)
Latency: 922219 -> 977997 (+6.05%)
InvThroughput: 212154 -> 201746 (-4.91%); split: -5.54%, +0.64%
VClause: 1120 -> 1155 (+3.12%); split: -1.88%, +5.00%
SClause: 1148 -> 1144 (-0.35%); split: -0.70%, +0.35%
Copies: 5840 -> 5788 (-0.89%); split: -0.94%, +0.05%
PreVGPRs: 753 -> 651 (-13.55%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16556>
2022-10-26 12:53:26 +00:00
Lionel Landwerlin
1d10d17817 nir/lower_shader_calls: add an option structure for future optimizations
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16556>
2022-10-26 12:53:25 +00:00
Samuel Pitoiset
db573f7362 aco: add support for device clock on GFX11
According to LLVM, s_sendmsg_rtn(GET_REALTIME) should be used instead
of s_memrealtime.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19267>
2022-10-25 20:23:08 +02:00
Samuel Pitoiset
c481978ac2 aco: split the sendmsg enumeration into sendmsg_rtn
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19267>
2022-10-25 20:23:07 +02:00
Samuel Pitoiset
6630b6e2aa aco: add support for s_sendmsg_rtn_b{32,64}
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19267>
2022-10-25 20:23:05 +02:00
Samuel Pitoiset
3a3df9acda ac/llvm: add support for device clock on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19267>
2022-10-25 20:22:48 +02:00
Rhys Perry
1c005e72f4 ac/nir: add legacy streamout and GS copy shader helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19302>
2022-10-25 17:35:08 +00:00
Rhys Perry
382831c986 radv,nir: add intrinsics for streamout and GS copy shaders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19302>
2022-10-25 17:35:08 +00:00
Qiang Yu
cf74cf3901 radeonsi: implement nir shader query enabled intrinsics
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17457>
2022-10-25 12:58:43 +00:00
Qiang Yu
540eafada1 ac/nir/ngg: add streamout emitted primitive query
For radeonsi to implement GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17457>
2022-10-25 12:58:43 +00:00
Qiang Yu
188a7f9226 ac/nir/ngg: add query param to ac_nir_lower_ngg_gs
radeonsi may disable it. gfx_level will also be used by latter
vertex param export when gfx11.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17457>
2022-10-25 12:58:43 +00:00
Qiang Yu
a119a6464f nir,ac,radv: add primitive count add intrinsics
radeonsi use shader buffer, but radv use gds for the query
result storage.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17457>
2022-10-25 12:58:43 +00:00
Samuel Pitoiset
e18f76d890 radv: disable dual source blending in more situations
According to PAL, there is more restrictions that RADV doesn't have.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19278>
2022-10-25 12:22:34 +00:00
Pierre-Eric Pelloux-Prayer
8034a71430 radeonsi/sqtt: re-export shaders in a single bo
RGP expects a pipeline's shaders to be all stored sequentially, eg:

  [vs][ps][gs]

As such, it assumes a single bo is dumped to the .rgp file, with
the following info:
  * va of the bo
  * offset to each shader inside the bo

For radeonsi, the shaders are stored individually, so we may have
a big gap between the shaders forming a pipeline => we can produce
very large file because the layout in the file must match the one
in memory (see the warning in ac_rgp_file_write_elf_text).

This commit implements a workaround: gfx shaders are re-exported as a
pipeline.

To update the shader address, a new state is created (sqtt_pipeline),
which will overwrite the needed _PGM_LO_* registers.

This reduces DeuxEX rgp captures from 150GB+ to less than 100MB.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18865>
2022-10-25 11:58:07 +00:00
Daniel Schürmann
a36e27e507 aco: change thread_local memory resource to pointer
Apparently the TLS constructor doesn't work well if RADV
is instantiated multiple times and/or used by a program with
already existing threads.

Fixes: a128d444cb ('aco: use monotonic_buffer_resource for instructions')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19219>
2022-10-25 09:08:08 +00:00
Qiang Yu
7ee0b8b8df ac/nir/ngg,radv: use different counters for shader queries
VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT should count for each
stream.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7409
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19015>
2022-10-25 02:42:52 +00:00
Qiang Yu
83643e4dc8 nir,ac/nir/ngg,radv: split shader_query_enabled_amd
For used by different counter.

Vulkan:
1. VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT,
   sum generated primitives of all 4 streams when GS.
2. VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT, count generated
   primitives for all 4 streams when VS/TES/GS.
3. VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT, count generated
   and streamout primitives for all 4 streams when VS/TES/GS.

OpenGL:
1. GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB, sum generated
   primitives for all 4 streams when GS.
2. GL_PRIMITIVES_GENERATED, count generated primitives for all 4
   streams when VS/TES/GS.
3. GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN, count streamout
   primitives for all 4 streams when VS/TES/GS.

pipeline_stat_query_enabled_amd is for Vulkan 1 and OpenGL 1.
xfb_query_enabled_amd is for Vulkan 2/3 and OpenGL 2/3.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19015>
2022-10-25 02:42:52 +00:00
Qiang Yu
1dcbf25757 radv: split active_pipeline_gds_queries
For different enabling of pipeline stat and prims gen.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19015>
2022-10-25 02:42:52 +00:00
Qiang Yu
0bbe8029b6 radv: count gen_prims_queries_enabled
User can enable/disable multi VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT
queries with same or different index.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19015>
2022-10-25 02:42:52 +00:00
Timur Kristóf
a17e801a9c aco: Add ACO_DEBUG=novalidateir option.
This disables IR validation in debug/debugoptimized builds.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18103>
2022-10-24 20:14:16 +00:00
Timur Kristóf
0cceab788e aco: Move is_dead to aco_ir.h to allow it to get inlined.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18103>
2022-10-24 20:14:16 +00:00
Timur Kristóf
36bc3afb8b aco/optimizer_postRA: Delete dead instructions more efficiently.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18103>
2022-10-24 20:14:16 +00:00
Timur Kristóf
7263a29794 aco/optimizer_postRA: Properly handle vccz/execz/scc in reset_block.
Fixes: a8dd07518c
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18103>
2022-10-24 20:14:16 +00:00
Timur Kristóf
75967a4814 aco/optimizer_postRA: Speed up reset_block() with predecessors.
Copy the information from the first predecessor then check whether
it matches other predecessors and modify the data accordingly.

Marked for backporting to stable to make it possible to also
backport fixes based on this.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18103>
2022-10-24 20:14:16 +00:00
Timur Kristóf
b542ab0243 aco/optimizer_postRA: Use unique_ptr + array for instruction indices.
According to perf, this roughly halves the impact of the post-RA
optimizer in ACO's compile times.

Measurement was taken using a debug optimized build using
NIR_DEBUG=novalidate RADV_DEBUG=nocache and replaying the Fossil DB
from the Doom Eternal shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18103>
2022-10-24 20:14:16 +00:00
Georg Lehmann
31c1cb06ad radv: Use available dot product instructions on gfx11.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19114>
2022-10-24 19:07:16 +00:00
Georg Lehmann
361b47b1f0 aco: Implement signed idot instructions on GFX11.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19114>
2022-10-24 19:07:16 +00:00
Georg Lehmann
cea6723243 ac/llvm: Implement signed idot on GFX11.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19114>
2022-10-24 19:07:16 +00:00
Georg Lehmann
616d3908dc aco: Don't use opsel for p_insert.
This doesn't make sense, opsel preserves the not selected half of the register,
p_insert zeros it.

No Foz-DB changes.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

Fixes: 54292e99c7 ("aco: optimize 32-bit extracts and inserts using SDWA")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19253>
2022-10-24 18:40:40 +00:00
Georg Lehmann
79a8a7662b aco: fmaak/fmamk can't use SDWA.
Found by inspection.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19255>
2022-10-24 18:04:53 +00:00
Yonggang Luo
224e501210 aco: Do not define NOMINMAX as it's already defined in pre_args now
It's a revert of fcd53bebe6 ("aco: Define NOMINMAX in Meson build file")
Because 852d91edcd ("windows: Always set NOMINMAX to remove min/max macros")
did the same thing

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19233>
2022-10-24 17:00:58 +00:00
Konstantin Seurer
ac01f09d57 radv/rt: Load instance id and custom index on demand
Stats for Quae II RTX:

57fps -> 57fps

Totals from 7 (14.00% of 50) affected shaders:
VGPRs: 800 -> 784 (-2.00%)
CodeSize: 217868 -> 218308 (+0.20%)
MaxWaves: 62 -> 63 (+1.61%)
Instrs: 40384 -> 40420 (+0.09%); split: -0.01%, +0.10%
Latency: 866315 -> 870692 (+0.51%)
InvThroughput: 199189 -> 196595 (-1.30%); split: -1.75%, +0.45%
VClause: 1058 -> 1077 (+1.80%)
SClause: 1126 -> 1130 (+0.36%)
Copies: 5787 -> 5772 (-0.26%); split: -0.40%, +0.14%
PreVGPRs: 764 -> 750 (-1.83%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19159>
2022-10-24 14:39:25 +00:00
Daniel Schürmann
6fcabb3b02 aco/ra: only rename fixed Operands if the copy-location matches
With epilogs, the same Operand can be fixed to multiple registers.

Fixes: 061b8bfd29 ('aco/ra: rework fixed operands')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18485>
2022-10-24 13:12:34 +00:00
Samuel Pitoiset
cf7ada973a radv: disable shaderBufferFloat64AtomicMinMax on GFX11
buffer_atomic_{fmin,fmax}_x2 aren't supported on this GPU apparently.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19268>
2022-10-24 12:40:33 +00:00
Samuel Pitoiset
7298bc1810 radv: disable {shader,sparse}ImageFloat32AtomicMinMax on GFX11
image_atomic_{fmin,fmax} aren't supported on this GPU apparently.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19268>
2022-10-24 12:40:33 +00:00
Samuel Pitoiset
1ec5b6774d ac: fix has_vrs_ds_export_bug for VanGogh
Missed it.

Fixes: 0a8a9d9d63 ("ac: add radeon_info::has_vrs_ds_export_bug")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19272>
2022-10-24 12:01:52 +00:00
Rhys Perry
f32dde2902 aco: swap v_perm_b32 operands
I misread the ISA doc and got the order wrong.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: dae1629778 ("aco: disable sdwa on gfx11")
Fixes: e68e6c75ca ("aco: use v_perm_b32 to copy 0xff00/0x00ff/0xff/0x00")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19223>
2022-10-24 10:52:56 +00:00
Bas Nieuwenhuizen
514a9b3b75 radv: Use correct primgrp size for gfx11.
From radeonsi, found by inspection.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19222>
2022-10-24 09:08:42 +00:00
Bas Nieuwenhuizen
9d782e5294 radv: Improve gfx11 clear colors for DCC.
When I wrote the function I did unorms wrong. Let's copy radeonsi
harder.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19222>
2022-10-24 09:08:42 +00:00
Pierre-Eric Pelloux-Prayer
434e74e658 radeonsi: zero init using the correct components count
This fixes the replay of the trace attached to
https://gitlab.freedesktop.org/mesa/mesa/-/issues/7530 which
would otherwise fail with an LLVM error:
  "All operands to PHI node must be the same type as the PHI node!"

Fixes: ae4379d81e ("ac/nir: export some undef as zero")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19189>
2022-10-24 09:33:48 +02:00
Samuel Pitoiset
152b90efcd aco,radv/llvm: do not export parameters on GFX11
They will be exported through the attribute ring instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19216>
2022-10-24 07:55:06 +02:00
Samuel Pitoiset
c5bf63753d ac/nir,radv/llvm: add support for the attribute ring
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19216>
2022-10-24 07:55:06 +02:00
Samuel Pitoiset
fee5e379f4 radv/llvm: do not set COMPR for exports on GFX11
Use 0x3 channel mask instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19216>
2022-10-24 07:53:59 +02:00