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nir/lower_shader_calls: add an option structure for future optimizations

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16556>
This commit is contained in:
Lionel Landwerlin 2022-10-19 16:33:20 +03:00 • committed by Marge Bot
parent d0543bfbec
commit 1d10d17817
4 changed files with 28 additions and 12 deletions
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6
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -1620,9 +1620,13 @@ create_rt_shader(struct radv_device *device, const VkRayTracingPipelineCreateInf
*/
NIR_PASS_V(nir_stage, move_rt_instructions);
const nir_lower_shader_calls_options opts = {
.address_format = nir_address_format_32bit_offset,
.stack_alignment = 16,
};
uint32_t num_resume_shaders = 0;
nir_shader **resume_shaders = NULL;
nir_lower_shader_calls(nir_stage, nir_address_format_32bit_offset, 16, &resume_shaders,
nir_lower_shader_calls(nir_stage, &opts, &resume_shaders,
&num_resume_shaders, nir_stage);
vars.stage_idx = i;

11
src/compiler/nir/nir.h
View file

@ -4834,10 +4834,17 @@ bool nir_lower_explicit_io(nir_shader *shader,
nir_variable_mode modes,
nir_address_format);
typedef struct nir_lower_shader_calls_options {
/* Address format used for load/store operations on the call stack. */
nir_address_format address_format;
/* Stack alignment */
unsigned stack_alignment;
} nir_lower_shader_calls_options;
bool
nir_lower_shader_calls(nir_shader *shader,
nir_address_format address_format,
unsigned stack_alignment,
const nir_lower_shader_calls_options *options,
nir_shader ***resume_shaders_out,
uint32_t *num_resume_shaders_out,
void *mem_ctx);

14
src/compiler/nir/nir_lower_shader_calls.c
View file

@ -1424,8 +1424,7 @@ nir_opt_remove_respills(nir_shader *shader)
*/
bool
nir_lower_shader_calls(nir_shader *shader,
nir_address_format address_format,
unsigned stack_alignment,
const nir_lower_shader_calls_options *options,
nir_shader ***resume_shaders_out,
uint32_t *num_resume_shaders_out,
void *mem_ctx)
@ -1461,7 +1460,7 @@ nir_lower_shader_calls(nir_shader *shader,
}
NIR_PASS_V(shader, spill_ssa_defs_and_lower_shader_calls,
num_calls, stack_alignment);
num_calls, options->stack_alignment);
NIR_PASS_V(shader, nir_opt_remove_phis);
@ -1494,9 +1493,12 @@ nir_lower_shader_calls(nir_shader *shader,
for (unsigned i = 0; i < num_calls; i++)
NIR_PASS_V(resume_shaders[i], nir_opt_remove_respills);
NIR_PASS_V(shader, nir_lower_stack_to_scratch, address_format);
for (unsigned i = 0; i < num_calls; i++)
NIR_PASS_V(resume_shaders[i], nir_lower_stack_to_scratch, address_format);
NIR_PASS_V(shader, nir_lower_stack_to_scratch,
options->address_format);
for (unsigned i = 0; i < num_calls; i++) {
NIR_PASS_V(resume_shaders[i], nir_lower_stack_to_scratch,
options->address_format);
}
*resume_shaders_out = resume_shaders;
*num_resume_shaders_out = num_calls;

9
src/intel/vulkan/anv_pipeline.c
View file

@ -2465,9 +2465,12 @@ compile_upload_rt_shader(struct anv_ray_tracing_pipeline *pipeline,
nir_shader **resume_shaders = NULL;
uint32_t num_resume_shaders = 0;
if (nir->info.stage != MESA_SHADER_COMPUTE) {
NIR_PASS(_, nir, nir_lower_shader_calls,
nir_address_format_64bit_global,
BRW_BTD_STACK_ALIGN,
const nir_lower_shader_calls_options opts = {
.address_format = nir_address_format_64bit_global,
.stack_alignment = BRW_BTD_STACK_ALIGN,
};
NIR_PASS(_, nir, nir_lower_shader_calls, &opts,
&resume_shaders, &num_resume_shaders, mem_ctx);
NIR_PASS(_, nir, brw_nir_lower_shader_calls, &stage->key.bs);
NIR_PASS_V(nir, brw_nir_lower_rt_intrinsics, devinfo);