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ac/nir: add legacy streamout and GS copy shader helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19302>
This commit is contained in:
Rhys Perry
Marge Bot
parent
382831c986
commit
1c005e72f4
2 changed files with 226 additions and 0 deletions
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@ -108,3 +108,216 @@ ac_nir_lower_indirect_derefs(nir_shader *shader,
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NIR_PASS(progress, shader, nir_lower_indirect_derefs, indirect_mask, UINT32_MAX);
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return progress;
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}
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static void
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emit_streamout(nir_builder *b, const struct pipe_stream_output_info *info, unsigned stream,
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nir_ssa_def *const outputs[64][4])
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{
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nir_ssa_def *so_vtx_count = nir_ubfe_imm(b, nir_load_streamout_config_amd(b), 16, 7);
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nir_ssa_def *tid = nir_load_subgroup_invocation(b);
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nir_push_if(b, nir_ilt(b, tid, so_vtx_count));
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nir_ssa_def *so_write_index = nir_load_streamout_write_index_amd(b);
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nir_ssa_def *so_buffers[PIPE_MAX_SO_BUFFERS];
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nir_ssa_def *so_write_offset[PIPE_MAX_SO_BUFFERS];
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for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
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uint16_t stride = info->stride[i];
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if (!stride)
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continue;
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so_buffers[i] = nir_load_streamout_buffer_amd(b, i);
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nir_ssa_def *offset = nir_load_streamout_offset_amd(b, i);
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offset = nir_iadd(b, nir_imul_imm(b, nir_iadd(b, so_write_index, tid), stride * 4),
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nir_imul_imm(b, offset, 4));
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so_write_offset[i] = offset;
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}
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nir_ssa_def *undef = nir_ssa_undef(b, 1, 32);
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for (unsigned i = 0; i < info->num_outputs; i++) {
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const struct pipe_stream_output *output = &info->output[i];
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if (stream != output->stream)
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continue;
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nir_ssa_def *vec[4] = {undef, undef, undef, undef};
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uint8_t mask = 0;
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for (unsigned j = 0; j < output->num_components; j++) {
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if (outputs[output->register_index][output->start_component + j]) {
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vec[j] = outputs[output->register_index][output->start_component + j];
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mask |= 1 << j;
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}
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}
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if (!mask)
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continue;
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unsigned buffer = output->output_buffer;
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nir_ssa_def *data = nir_vec(b, vec, output->num_components);
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nir_ssa_def *zero = nir_imm_int(b, 0);
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nir_store_buffer_amd(b, data, so_buffers[buffer], so_write_offset[buffer], zero, zero,
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.base = output->dst_offset * 4, .slc_amd = true, .write_mask = mask,
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.access = ACCESS_COHERENT);
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}
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nir_pop_if(b, NULL);
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}
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nir_shader *
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ac_nir_create_gs_copy_shader(const nir_shader *gs_nir,
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const struct pipe_stream_output_info *so_info, size_t num_outputs,
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const uint8_t *output_usage_mask, const uint8_t *output_streams,
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const uint8_t *output_semantics,
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const uint8_t num_stream_output_components[4])
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{
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assert(num_outputs <= 64);
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nir_builder b = nir_builder_init_simple_shader(
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MESA_SHADER_VERTEX, gs_nir->options, "gs_copy");
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nir_foreach_shader_out_variable(var, gs_nir)
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nir_shader_add_variable(b.shader, nir_variable_clone(var, b.shader));
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nir_ssa_def *gsvs_ring = nir_load_ring_gsvs_amd(&b);
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nir_ssa_def *stream_id = NULL;
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if (so_info->num_outputs)
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stream_id = nir_ubfe_imm(&b, nir_load_streamout_config_amd(&b), 24, 2);
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nir_ssa_def *vtx_offset = nir_imul_imm(&b, nir_load_vertex_id_zero_base(&b), 4);
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nir_ssa_def *undef = nir_ssa_undef(&b, 1, 32);
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nir_ssa_def *zero = nir_imm_zero(&b, 1, 32);
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for (unsigned stream = 0; stream < 4; stream++) {
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if (stream > 0 && (!stream_id || !num_stream_output_components[stream]))
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continue;
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if (stream_id)
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nir_push_if(&b, nir_ieq_imm(&b, stream_id, stream));
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uint32_t offset = 0;
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uint64_t output_mask = 0;
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nir_ssa_def *outputs[64][4] = {{0}};
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for (unsigned i = 0; i < num_outputs; i++) {
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unsigned mask = output_usage_mask[i];
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if (!mask)
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continue;
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u_foreach_bit (j, mask) {
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if (((output_streams[i] >> (j * 2)) & 0x3) != stream)
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continue;
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outputs[i][j] = nir_load_buffer_amd(&b, 1, 32, gsvs_ring, vtx_offset, zero, zero,
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.base = offset, .is_swizzled = false,
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.slc_amd = true, .access = ACCESS_COHERENT);
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offset += gs_nir->info.gs.vertices_out * 16 * 4;
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}
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output_mask |= 1ull << i;
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}
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if (stream_id)
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emit_streamout(&b, so_info, stream, outputs);
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if (stream == 0) {
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u_foreach_bit64 (i, output_mask) {
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uint8_t mask = 0;
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nir_ssa_def *vec[4];
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for (unsigned j = 0; j < 4; j++) {
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vec[j] = outputs[i][j] ? outputs[i][j] : undef;
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mask |= (outputs[i][j] ? 1 : 0) << j;
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}
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gl_varying_slot location = output_semantics ? output_semantics[i] : i;
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nir_store_output(&b, nir_vec(&b, vec, 4), zero, .base = i, .write_mask = mask,
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.src_type = nir_type_uint32,
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.io_semantics = {.location = location, .num_slots = 1});
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}
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nir_export_vertex_amd(&b);
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}
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if (stream_id)
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nir_push_else(&b, NULL);
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}
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b.shader->info.clip_distance_array_size = gs_nir->info.clip_distance_array_size;
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b.shader->info.cull_distance_array_size = gs_nir->info.cull_distance_array_size;
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return b.shader;
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}
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static void
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gather_outputs(nir_builder *b, nir_function_impl *impl, nir_ssa_def *outputs[64][4])
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{
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/* Assume:
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* - the shader used nir_lower_io_to_temporaries
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* - 64-bit outputs are lowered
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* - no indirect indexing is present
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*/
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nir_foreach_block(block, impl) {
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nir_foreach_instr (instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic != nir_intrinsic_store_output)
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continue;
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assert(nir_src_is_const(intrin->src[1]) && !nir_src_as_uint(intrin->src[1]));
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unsigned slot = nir_intrinsic_base(intrin);
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u_foreach_bit (i, nir_intrinsic_write_mask(intrin)) {
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unsigned comp = nir_intrinsic_component(intrin) + i;
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outputs[slot][comp] = nir_channel(b, intrin->src[0].ssa, i);
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}
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}
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}
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}
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void
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ac_nir_lower_legacy_vs(nir_shader *nir, int primitive_id_location,
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const struct pipe_stream_output_info *so_info)
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{
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nir_function_impl *impl = nir_shader_get_entrypoint(nir);
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nir_metadata preserved = nir_metadata_block_index | nir_metadata_dominance;
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nir_builder b;
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nir_builder_init(&b, impl);
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b.cursor = nir_after_cf_list(&impl->body);
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if (primitive_id_location >= 0) {
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/* When the primitive ID is read by FS, we must ensure that it's exported by the previous
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* vertex stage because it's implicit for VS or TES (but required by the Vulkan spec for GS
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* or MS).
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*/
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nir_variable *var = nir_variable_create(nir, nir_var_shader_out, glsl_int_type(), NULL);
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var->data.location = VARYING_SLOT_PRIMITIVE_ID;
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var->data.interpolation = INTERP_MODE_NONE;
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var->data.driver_location = primitive_id_location;
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nir_store_output(
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&b, nir_load_primitive_id(&b), nir_imm_int(&b, 0), .base = primitive_id_location,
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.src_type = nir_type_int32,
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.io_semantics = (nir_io_semantics){.location = var->data.location, .num_slots = 1});
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/* Update outputs_written to reflect that the pass added a new output. */
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nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_ID);
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}
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if (so_info && so_info->num_outputs) {
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/* 26.1. Transform Feedback of Vulkan 1.3.229 spec:
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* > The size of each component of an output variable must be at least 32-bits.
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* We lower 64-bit outputs.
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*/
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nir_ssa_def *outputs[64][4] = {{0}};
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gather_outputs(&b, impl, outputs);
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emit_streamout(&b, so_info, 0, outputs);
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preserved = nir_metadata_none;
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}
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nir_export_vertex_amd(&b);
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nir_metadata_preserve(impl, preserved);
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}
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@ -27,9 +27,11 @@
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#define AC_NIR_H
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#include "nir.h"
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#include "nir_builder.h"
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#include "ac_shader_args.h"
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#include "ac_shader_util.h"
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#include "amd_family.h"
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#include "pipe/p_state.h"
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#ifdef __cplusplus
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extern "C" {
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@ -179,6 +181,17 @@ ac_nir_lower_global_access(nir_shader *shader);
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bool ac_nir_lower_resinfo(nir_shader *nir, enum amd_gfx_level gfx_level);
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nir_shader *
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ac_nir_create_gs_copy_shader(const nir_shader *gs_nir,
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const struct pipe_stream_output_info *so_info, size_t num_outputs,
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const uint8_t *output_usage_mask, const uint8_t *output_streams,
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const uint8_t *output_semantics,
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const uint8_t num_stream_output_components[4]);
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void
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ac_nir_lower_legacy_vs(nir_shader *nir, int primitive_id_location,
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const struct pipe_stream_output_info *so_info);
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#ifdef __cplusplus
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}
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#endif
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