Commit graph

11349 commits

Author SHA1 Message Date
Rhys Perry
928ecfc6c0 radv: fix RADV_DEBUG=shaderstats with RT pipelines
radv_dump_shader_stats() printed stats for every shader with a certain
stage, and we called this function each time an RT shader is compiled.

This means we could repeat the stats for a shader.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39484>
2026-01-26 09:26:14 +00:00
Samuel Pitoiset
c91ed27582 radv: use the SQTT enable bit for PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE
Some checks are pending
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39425>
2026-01-26 08:10:53 +00:00
Samuel Pitoiset
e272c8062d radv: use the SQTT enable bit for PKT3_DISPATCH_MESH_INDIRECT_MULTI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39425>
2026-01-26 08:10:53 +00:00
Samuel Pitoiset
c7da19e2bf radv: use the SQTT enable bit for PKT3_DRAW_{INDEX}_INDIRECT_MULTI
This reports more info in RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39425>
2026-01-26 08:10:52 +00:00
Samuel Pitoiset
e5982496f6 radv: move emitting SQTT markers closer to the draw/dispatch packets
Some packets already include a SQTT enable bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39425>
2026-01-26 08:10:52 +00:00
Georg Lehmann
763b4f1f0a radv/gfx11: add a RADV_PERFTEST flag to expose bfloat16 cmat
This doesn't pass CTS because of precision issues, but might still be useful.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14699
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39456>
2026-01-23 09:41:20 +00:00
jaap aarts
8f7941f92d radv/sqtt: Prevent concurrent submit when sqtt is enabled
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39090>
2026-01-21 18:55:56 +00:00
Timur Kristóf
fc0827126f radv: Remove previous mitigation of CS regalloc hang bug
Now that all larger workgroup sizes are lowered to 256,
the old workaround is not needed anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39288>
2026-01-21 17:24:57 +00:00
Timur Kristóf
86ff28b3da radv: Allow using compute queue with CS regalloc hang bug on GFX7
Now that all larger workgroup sizes are lowered to 256,
the regalloc hang cannot mess up the compute queues anymore.

Still don't allow compute queues on GFX6 though,
they are prone to hangs. Needs further investigation.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39288>
2026-01-21 17:24:56 +00:00
Timur Kristóf
d31b4451f2 radv: Lower larger workgroups to 256 for CS regalloc bug
This is the safest maximum workgroup size if we want to avoid
the hang on affected GPUs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39288>
2026-01-21 17:24:56 +00:00
Qiang Yu
4708eb85d7 radv: fix primitive restart gpu hang for pre gfx10
Some checks are pending
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PAL always set WD_SWITCH_ON_EOP for pre gfx10 when primitive
restart is enabled to prevent gpu hang.

It only happens when specific index stream with primitive
restart. Since we don't know what's the exact problem,
just follow PAL to disable 4x primitive rate when primitive
restart is enabled.

GFX10+ does not use this function.

Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39292>
2026-01-21 02:38:26 +00:00
Natalie Vock
30f6eacfad radv/rt: Call ahit/isec shaders
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:55 +00:00
Natalie Vock
a03e9287c3 radv/rt: Compile ahit/isec shaders to asm
We can express any-hit/intersection shaders as functions, too.
Any-hit/Intersection shaders need the usual parameters like launch
IDs/descriptor data/ray properties, origin, direction/etc., but also
some special parameters related to traversal state. Any-hit/intersection
shaders need to return whether the hit was accepted and/or traversal
should be terminated, as well as the intersection T value (for
intersection shaders). Both any-hit and intersection shaders also need
to be passed hit attributes via parameters. Closest-Hit shaders need
those too, but we pass them out-of-band via LDS. LDS is used for the
traversal stack when any-hit/intersection shaders, so we need to pass
them via parameters.

Hit attributes are similar to ray payloads in the sense that they're
dynamically sized depending on how much space the application uses.
However, unlike ray payloads, hit attribute sizes have a strict upper
bound of 8 dwords. To make managing parameters easier, we put all hit
attributes in a single vector parameter with 0-8 components. This
prevents having a function with two sets of arbitrary numbers of
parameters.

This commit sets up ahit/isec function signatures and implements
lowering for ahit/isec-specific intrinsics in the context of these
functions. Subsequent commits will merely have to call into these
functions to execute a separate-compiled any-hit/intersection shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:55 +00:00
Natalie Vock
e74e0983a7 radv/rt: Fix terminate_ray handling for intersection shaders
terminate_ray should only return from any-hit shaders, it should not
skip the intersection shader. If we insert a nir_jump_return when
processing the already-inlined any-hit shader, the intersection shader
will be skipped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Natalie Vock
646d3b9645 radv/nir: Make nir_lower_intersection_shader public
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Natalie Vock
1fb005b487 radv/nir: Add and use radv_nir_return_param_from_type helper
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Natalie Vock
bde7bebc01 radv/rt: Don't consider non-internal INTERSECTION shaders as the traversal shader
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Samuel Pitoiset
71f5434142 radv: optimize layered fast clear colors when comp-to-single is supported
comp-to-single is supported since GFX10, it's a new type of DCC fast
clear which doesn't require FCE and doesn't require to set fast clear
registers (ie. comp-to-reg). This means that it's possible to fast clear
even if not all slices are bound, because the clear code is stored in
the main image.

This improves performance in Dirt Rally 2.0 by +2-5%. Other games that
have layered clears would also benefit on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39394>
2026-01-20 18:28:59 +00:00
Samuel Pitoiset
8781dd85c2 radv/meta: add support for fast clearing color images with non-zero baseArrayLayer
Like vkCmdClearAttachments(). This is a preliminary change for the
next commit which will enable these fast clears when comp-to-single
is supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39394>
2026-01-20 18:28:59 +00:00
Icenowy Zheng
734b6a8c35 vk: descriptors: sort bindings along with flags
Some checks are pending
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Vulkan spec requires binding flags to be matched with the binding with
the same index, however currently bindings are sorted with flags not
properly sorted, which leads to bindings and flags mismatch.

Resolve this by adding optional flags info to the parameters of
vk_create_sorted_bindings(), and refactoring panvk/pvr (which really
pair bindings and flags instead of only iterating flags) to use sorted
flags.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38967>
2026-01-20 15:55:47 +00:00
Samuel Pitoiset
3e7f38efa8 radv: always fast-clear color image with comp-to-single on GFX11-11.5
This is possible because no comp-to-reg and no FCE. This probably helps
a bunch on GFX11+ if GENERAL is widely used with color images. And
since VK_KHR_unified_image_layout it's likely the case on GFX11-11.5

GFX10-10.3 could also benefit from this but some MSAA with DCC
fast-clears are currently broken and they need to be fixed first.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39396>
2026-01-20 15:15:35 +00:00
Georg Lehmann
711598982a ac/nir,radv: remove ac_nir_opt_pack_half
Foz-DB Navi21:
Totals from 2937 (3.01% of 97591) affected shaders:
Instrs: 1908695 -> 1908291 (-0.02%); split: -0.02%, +0.00%
CodeSize: 10232148 -> 10229224 (-0.03%); split: -0.03%, +0.01%
VGPRs: 142168 -> 142080 (-0.06%)
Latency: 8052895 -> 8052622 (-0.00%); split: -0.01%, +0.01%
InvThroughput: 2550330 -> 2549602 (-0.03%); split: -0.03%, +0.01%
VClause: 32601 -> 32603 (+0.01%); split: -0.01%, +0.02%
Copies: 118570 -> 118587 (+0.01%); split: -0.04%, +0.05%
PreVGPRs: 110090 -> 110082 (-0.01%)
VALU: 1468422 -> 1468043 (-0.03%); split: -0.03%, +0.00%
SALU: 173858 -> 173828 (-0.02%)

Foz-DB Navi48:
Totals from 4196 (4.30% of 97637) affected shaders:
MaxWaves: 118678 -> 118680 (+0.00%); split: +0.01%, -0.01%
Instrs: 3627604 -> 3624093 (-0.10%); split: -0.10%, +0.00%
CodeSize: 18956684 -> 18939824 (-0.09%); split: -0.09%, +0.01%
VGPRs: 225624 -> 225060 (-0.25%); split: -0.26%, +0.01%
Latency: 11856204 -> 11857280 (+0.01%); split: -0.01%, +0.02%
InvThroughput: 2388584 -> 2389178 (+0.02%); split: -0.01%, +0.03%
VClause: 50409 -> 50410 (+0.00%)
SClause: 64701 -> 64699 (-0.00%)
Copies: 208353 -> 207522 (-0.40%); split: -0.43%, +0.03%
PreVGPRs: 161314 -> 161306 (-0.00%)
VALU: 2345604 -> 2345172 (-0.02%); split: -0.02%, +0.00%
SALU: 391466 -> 388723 (-0.70%)
VOPD: 1788 -> 1806 (+1.01%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38815>
2026-01-20 14:48:23 +00:00
Marek Olšák
f8f4c02c97 radv: rename hiz_his to gfx12_*hiz
Only GFX12 will ever have this.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39260>
2026-01-19 16:58:17 +00:00
Marek Olšák
482c410f41 ac: remove never enabled gfx12 HiS
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39260>
2026-01-19 16:58:17 +00:00
Rhys Perry
f5f2f9110c radv/rt: lower non-return load_param to variable loads
nir_intrinsic_load_param can't be CSE'd, which can prevent phi cleanup
and potentially unneeded scratch access.

fossil-db (navi31):
Totals from 4 (0.01% of 79825) affected shaders:
Instrs: 2504 -> 2384 (-4.79%)
CodeSize: 13584 -> 12784 (-5.89%)
Latency: 96124 -> 96056 (-0.07%)
InvThroughput: 12016 -> 12008 (-0.07%)
Copies: 664 -> 504 (-24.10%)
Branches: 92 -> 88 (-4.35%)
VALU: 1232 -> 1112 (-9.74%)
VOPD: 308 -> 228 (-25.97%)

fossil-db (navi31, monolithic pipelines disabled):
Totals from 52 (0.06% of 80095) affected shaders:
Instrs: 126296 -> 124734 (-1.24%)
CodeSize: 718272 -> 707864 (-1.45%)
Latency: 2866019 -> 2865125 (-0.03%)
InvThroughput: 502663 -> 502537 (-0.03%)
Copies: 19616 -> 17536 (-10.60%)
Branches: 4344 -> 4292 (-1.20%)
VALU: 65432 -> 63872 (-2.38%)
VOPD: 14543 -> 13503 (-7.15%)

fossil-db (navi31, monolithic pipelines disabled, any-hit function calls):
Totals from 52 (0.06% of 80304) affected shaders:
Instrs: 38232 -> 34956 (-8.57%)
CodeSize: 184616 -> 171400 (-7.16%)
Latency: 944112 -> 941483 (-0.28%)
InvThroughput: 122152 -> 121817 (-0.27%)
Copies: 13065 -> 10302 (-21.15%)
Branches: 1471 -> 1419 (-3.54%)
PreSGPRs: 2673 -> 2598 (-2.81%)
VALU: 22576 -> 19368 (-14.21%)
SALU: 6549 -> 6474 (-1.15%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39344>
2026-01-19 08:55:39 +00:00
Rhys Perry
37b956a203 radv/rt: cleanup phis after lowering parameter variables to SSA
No fossil-db changes.

fossil-db (navi31, monolithic pipelines disabled):
Totals from 21 (0.03% of 80095) affected shaders:
MaxWaves: 312 -> 320 (+2.56%)
Instrs: 9989 -> 9666 (-3.23%)
CodeSize: 56020 -> 53696 (-4.15%)
VGPRs: 1488 -> 1440 (-3.23%)
Latency: 157965 -> 146639 (-7.17%)
InvThroughput: 25192 -> 22390 (-11.12%)
VClause: 186 -> 148 (-20.43%)
PreVGPRs: 1196 -> 1147 (-4.10%)
VALU: 5053 -> 5040 (-0.26%)
VMEM: 506 -> 240 (-52.57%)
VOPD: 992 -> 1005 (+1.31%)

fossil-db (navi31, monolithic pipelines disabled, any-hit function calls):
Totals from 41 (0.05% of 80304) affected shaders:
Instrs: 20615 -> 20436 (-0.87%); split: -0.97%, +0.10%
CodeSize: 98780 -> 98080 (-0.71%); split: -0.79%, +0.09%
Latency: 341542 -> 341796 (+0.07%); split: -0.05%, +0.13%
InvThroughput: 46353 -> 46386 (+0.07%); split: -0.05%, +0.12%
Copies: 6958 -> 6818 (-2.01%); split: -2.41%, +0.40%
Branches: 676 -> 657 (-2.81%)
VALU: 12232 -> 12092 (-1.14%); split: -1.37%, +0.23%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39344>
2026-01-19 08:55:39 +00:00
Samuel Pitoiset
91a5a0f2b9 radv/meta: fix layered depth stencil resolves with compute
Some checks are pending
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Fixes a bunch of new VKCTS coverage like
dEQP-VK.pipeline.monolithic.multisample.m10_resolve.resolve_cmd.d32_sfloat.depth.average.full_multilayer.no_flags

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39349>
2026-01-19 07:22:26 +00:00
Konstantin Seurer
091b43b970 radv: Use HPLOC for TLAS builds
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The BVH quality is comparable to PLOC but the build is much faster.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39116>
2026-01-18 19:21:08 +01:00
Mauro Rossi
197cb437cd radv/rt: Fix gnu-empty-initializer error in radv_pipeline_rt.c
Some checks are pending
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Fixes the following building error happening with clang:

FAILED: src/amd/vulkan/libvulkan_radeon.so.p/radv_pipeline_rt.c.o
...
../src/amd/vulkan/radv_pipeline_rt.c:934:38: error: use of GNU empty initializer extension [-Werror,-Wgnu-empty-initializer]
   struct nir_function raygen_stub = {};
                                     ^
1 error generated.

Fixes: 0a1911b2 ("radv,aco: Use function call structure for RT programs")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39370>
2026-01-17 17:13:05 +01:00
Samuel Pitoiset
5555297121 radv/meta: always use mip level 0 for source image resolves
MSAA+mipmaps isn't a thing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39285>
2026-01-16 11:35:34 +00:00
Samuel Pitoiset
cb57338d6f radv/meta: batch resolving all color image layers with compute
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39285>
2026-01-16 11:35:34 +00:00
Samuel Pitoiset
1199f91a2f radv/meta: use 2D array for color resolves with compute
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39285>
2026-01-16 11:35:34 +00:00
Samuel Pitoiset
cb7e1859d7 radv/sqtt: fail if GPU clocks can't be sampled
All timing would be wrong otherwise, this should be considered a real
error.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39311>
2026-01-16 08:30:32 +00:00
Samuel Pitoiset
feed5fbc71 radv/sqtt: delay VMID reservation at capture time
If two devices/instances are created, the VMID reservation will just
fail. It seems fine as long as it's reserved before SPM is used.

Fixes: a7a4abc8d8 ("radv: Move VMID reservation to vkCreateDevice")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39311>
2026-01-16 08:30:32 +00:00
Emma Anholt
b375da7f2a nir: Let nir_eval_const_opcode() return a poison mask in case of UB.
This is unused by any callers currently, but will be useful for nir
algebraic pattern testing, and as a way to turn our comments in
nir_opcodes.py into actual C code.  For now, always returns false.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39076>
2026-01-15 19:09:32 +00:00
Benjamin Cheng
371656de90 radv/video_enc: Remove CTS WA
This has been fixed in CTS since ebe05a88f36e3be8e232bfce97812353c396674a.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39242>
2026-01-15 11:45:33 +00:00
Marek Olšák
fa88c65bb8 radv,radeonsi: don't set LINE_STIPPLE_TEX_ENA on gfx12
Fixes: 3c5c96fedb - radv: double pixel throughput in certain cases of PS without interpolated inputs
Fixes: 5acabdd1f8 - radeonsi: double pixel throughput in certain cases of PS without inputs
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14646

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39316>
2026-01-15 09:12:13 +00:00
Samuel Pitoiset
c559042a2a radv/dgc: adjust task+mesh SQTT markers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39178>
2026-01-15 09:43:00 +01:00
Samuel Pitoiset
82d00a4963 radv: fix missing SQTT markers for task+mesh draws
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39178>
2026-01-15 09:43:00 +01:00
Samuel Pitoiset
aee006efcd radv/sqtt: emit userdata in the gang CS when needed
For task shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39178>
2026-01-15 09:43:00 +01:00
Samuel Pitoiset
4da2e971e6 radv/sqtt: rework radv_emit_sqtt_userdata() to support gang CS
For task shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39178>
2026-01-15 09:42:59 +01:00
Natalie Vock
6f076cdfda radv: Use wave32 for RT on gfx11+
ACO got a lot better at forming VOPD instructions, and testing
feedback seems to point in a slightly positive direction for this.

gfx12 will also start requiring wave32 for dynamic VGPR allocation at
some point.

Measurements on navi31:

Cyberpunk 2077:
Difference at 95.0% confidence
        1.12333 +/- 0.42876
        1.88216% +/- 0.718391%
        (Student's t, pooled s = 0.189165)

Black Myth Wukong benchmark:
Difference at 95.0% confidence
        4 +/- 1.30862
        13.9535% +/- 4.56495%
        (Student's t, pooled s = 0.57735)

Portal with RTX:
66.2ms->61.5ms (~7.64% improvement)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39275>
2026-01-14 23:39:24 +00:00
Natalie Vock
27c0326391 radv: Re-enable RT pipelines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:07 +00:00
Natalie Vock
0a1911b220 radv,aco: Use function call structure for RT programs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:07 +00:00
Natalie Vock
c5d796c902 radv/rt: Use function call structure in NIR lowering
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:06 +00:00
Natalie Vock
d3cb8b4046 radv: Refactor RT lowering decisions and add RADV_PERFTEST CPS override
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:06 +00:00
Natalie Vock
63c019f5be radv: Temporarily disable RT pipelines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Natalie Vock
d563415100 radv: Add traversal stack size to cache
We just... didn't do this at all??? I have no idea how this didn't blow
up before, given that plenty of apps should generate a traversal shader
that spills (and thus has a large stack size), but it did finally blow
up in function-call related work.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Alyssa Rosenzweig
e98728de3c radv: cleanup texture builder
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39271>
2026-01-14 08:18:15 +00:00
Samuel Pitoiset
14deea2633 radv: enable SPM for GFX11.5
This adds support for performance counters with RGP on GFX11.5.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39270>
2026-01-13 22:16:40 +00:00