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Author SHA1 Message Date
Samuel Pitoiset
90d9f9a37e aco: remove unecessary p_split_vector with v2b reg class 
Should be fine now that RA take full registers for v2b if it's
not an SDWA instruction.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4879>
 2020-05-05 08:50:10 +02:00
Joshua Ashton
b0cb38f360 vulkan: Update Vulkan XML and headers to 1.2.140 
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
 2020-05-05 00:28:00 +00:00
Joshua Ashton
785803a2e5 turnip: Remove RANGE_SIZE usage 
These were removed from the latest Vulkan headers
https://github.com/KhronosGroup/Vulkan-Docs/issues/1230

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
 2020-05-05 00:28:00 +00:00
Joshua Ashton
24f9aea770 radv: Remove RANGE_SIZE usage 
These were removed from the latest Vulkan headers
https://github.com/KhronosGroup/Vulkan-Docs/issues/1230

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
 2020-05-05 00:28:00 +00:00
Joshua Ashton
c4d11ea3c4 anv: Remove RANGE_SIZE usage 
These were removed from the latest Vulkan headers
https://github.com/KhronosGroup/Vulkan-Docs/issues/1230

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
 2020-05-05 00:27:59 +00:00
Mauro Rossi
5779694698 android: iris: add iris_seqno.{c,h} to Makefile.sources 
Fixes the following undefined symbol building errors:

ld.lld: error: undefined symbol: iris_seqno_init
>>> referenced by iris_batch.c:187 (external/mesa/src/gallium/drivers/iris/iris_batch.c:187)
>>>               iris_batch.o:(iris_init_batch) in archive out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_iris_intermediates/libmesa_pipe_iris.a

Fixes: e31b703c ("iris: Place a seqno at the end of every batch")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
 2020-05-04 22:33:04 +02:00
Marek Olšák
c4cdef64ad ac/surface: fix MSAA crash with FORCE_SWIZZLE_MODE on gfx9 
Fixes: 3dc2ccc14c "ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODE"

Closes: #2884

Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4862>
 2020-05-04 20:03:15 +00:00
Alyssa Rosenzweig
1dcf291e3b pan/bit: Add IMATH packing tests 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
8fcc23bf28 pan/bit: Factor out identity swizzle helper 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
36e4ffa382 pan/bit: Use swizzle helper for round 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
118d53bf93 pan/bit: Remove test names 
We already have the disasm which is authoritative.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
52cdaaacbb pan/bit: Interpret v4i8 ops 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
66163614db pan/bit: Interpret IMATH 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
1799435df0 pan/bi: Don't schedule <32-bit IMATH to FMA 
The ops don't exist.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
2925e88996 pan/bi: Add SUB.v2i16/SUB.v4i8 opcodes to disasm 
Like their ADD counterparts. Only on ADD.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
10c18c6f69 pan/bi: Pack ADD IADD/ISUB for 8/16/32 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
a463b2c2ed pan/bi: Pack FMA IADD/ISUB 32 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
cf3c3563e0 pan/bi: Use IMATH for nir_op_iadd 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Alyssa Rosenzweig
1a94daef58 pan/bi: Rename BI_ISUB to BI_IMATH 
We'll use this for iadd, etc too which share similar characteristics.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
 2020-05-04 18:45:15 +00:00
Eric Anholt
5c81f51c3c freedreno/ir3: Define the bindful uniform/nonuniform desc modes for cat6 a6xx. 
These come from the disasm tests, and fix our disasm of blob's
uniform/nonuniform cat6 operands.  We also now include human-readable names
for all the modes we know about (though bindless gets distinguished by its
.baseN, like Connor's original disasm).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
 2020-05-04 11:15:50 -07:00
Eric Anholt
97b21110b8 freedreno/ir3: Sync some new changes from envytools. 
With this I also brought in a few new control flow instruction disasm
tests that I'd made back when I wrote the disasm test, but which were too
far from correct to include until now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
 2020-05-04 11:14:46 -07:00
Eric Anholt
1e5b0c92c5 freedreno/ir3: Add some more tests of cat6 disasm. 
I put these together from traces I had while trying to do LDC for GL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
 2020-05-04 11:14:46 -07:00
Marek Olšák
b97cc41aa2 Revert "ac: reassociate FP expressions for inexact instructions for radeonsi" 
This reverts commit cf2f3c2753.

It breaks shadows in Unigine Superposition.

Fixes: cf2f3c2753

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4837>
 2020-05-04 11:51:37 -04:00
Alyssa Rosenzweig
5f01869f74 pan/bit: Add ICMP tests 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
9bc684cad8 pan/bit: Add more 16-bit fmod tests 
Swizzles and more abs.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
041ba62e87 pan/bit: Add swizzles to round tests 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
35c806e701 pan/bi: Don't pack ICMP on FMA 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
5cbdf29b7e pan/bi: Pack ADD ICMP 16 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
5bd4172280 pan/bi: Pack ADD ICMP 32 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
336d5128f9 pan/bi: Structify ADD ICMP 16 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
fdf154d24a pan/bi: Pack ADD.DISCARD 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
7a9b9859e7 pan/bi: Handle discard/branch in get_component_count 
No dest requires special handling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:16 -04:00
Alyssa Rosenzweig
8ab5c97895 pan/bi: Fuse conditions into discard_if 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
201a11a13a pan/bi: Add float-only mode to condition fusing 
Useful for discards.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
7d867f787f pan/bi: Emit discard (not if) 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
c9ab73296c pan/bi: Handle discard_if in NIR->BIR naively 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
6627b20de3 pan/bi: Unwrap BRANCH into CONDITIONAL class 
We can simplify the IR considerably and unify more conditions, which
gives conditional discard for free.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
6e5d207293 pan/bi: Remove BI_GENERIC 
Goofy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
20cb039457 pan/bi: Structify DISCARD 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
5c03340fd1 pan/bi: Fix DISCARD ops in disasm 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
31a41bb6a6 pan/bi: Disable CSEL4 emit for now 
We need proper scheduling for 4-src ops to work, so for now disable
condition fusing so we cap at 3-src at a performance penalty. A bit of a
hack but I'd rather not build hacks into a scheduler that will be
rewritten soon anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
e14e3065a9 pan/bi: Fix incorrectly flipped swizzle 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
8415b3d552 pan/bi: Fix missing swizzle 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
c9634894a6 pan/bi: Fix double-abs flipping 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
ef9b4b3a0b pan/bi: Set clause type for gl_FragCoord.z 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:15 -04:00
Alyssa Rosenzweig
47c84ee735 pan/bi: Lower gl_FragCoord 
We accept a sysval and emit various forms for each component.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:14 -04:00
Alyssa Rosenzweig
c5ef35c433 pan/bi: Passthrough direct ld_var addresses 
Don't bother wasting a constant.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:14 -04:00
Alyssa Rosenzweig
513c774d58 pan/bi: Print bad instruction on src packing fail 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:14 -04:00
Alyssa Rosenzweig
0561fe3a06 pan/bi: Futureproof COMBINE lowering against non-u32 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:14 -04:00
Alyssa Rosenzweig
c48839086d pan/bi: Abort on unhandled intrinsics 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
 2020-05-04 11:08:14 -04:00