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pan/bi: Pack ADD IADD/ISUB for 8/16/32

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Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
This commit is contained in:
Alyssa Rosenzweig 2020-05-04 14:37:04 -04:00 • committed by Marge Bot
parent a463b2c2ed
commit 10c18c6f69
2 changed files with 35 additions and 0 deletions
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28
src/panfrost/bifrost/bi_pack.c
View file

@ -1625,6 +1625,32 @@ bi_pack_add_cmp(bi_instruction *ins, struct bi_registers *regs)
}
}
static unsigned
bi_pack_add_imath(bi_instruction *ins, struct bi_registers *regs)
{
/* TODO: 32+16 add */
assert(ins->src_types[0] == ins->src_types[1]);
unsigned sz = nir_alu_type_get_type_size(ins->src_types[0]);
enum bi_imath_op p = ins->op.imath;
unsigned op = 0;
if (sz == 8) {
op = (p == BI_IMATH_ADD) ? BIFROST_ADD_IADD_8 :
BIFROST_ADD_ISUB_8;
} else if (sz == 16) {
op = (p == BI_IMATH_ADD) ? BIFROST_ADD_IADD_16 :
BIFROST_ADD_ISUB_16;
} else if (sz == 32) {
op = (p == BI_IMATH_ADD) ? BIFROST_ADD_IADD_32 :
BIFROST_ADD_ISUB_32;
} else {
unreachable("64-bit todo");
}
return bi_pack_add_2src(ins, regs, op);
}
static unsigned
bi_pack_add(bi_clause *clause, bi_bundle bundle, struct bi_registers *regs)
{
@ -1649,7 +1675,9 @@ bi_pack_add(bi_clause *clause, bi_bundle bundle, struct bi_registers *regs)
case BI_DISCARD:
return bi_pack_add_discard(bundle.add, regs);
case BI_FREXP:
unreachable("Packing todo");
case BI_IMATH:
return bi_pack_add_imath(bundle.add, regs);
case BI_LOAD:
unreachable("Packing todo");
case BI_LOAD_ATTR:

7
src/panfrost/bifrost/bifrost.h
View file

@ -195,6 +195,13 @@ struct bifrost_add_discard {
#define BIFROST_ADD_OP_LD_UBO_4 (0x0c220 >> 3)
#define BIFROST_ADD_SEL_16(swiz) ((0xea60 >> 3) | (swiz))
#define BIFROST_ADD_IADD_8 (0x17880 >> 3)
#define BIFROST_ADD_IADD_16 (0x17900 >> 3)
#define BIFROST_ADD_IADD_32 (0x178c0 >> 3)
#define BIFROST_ADD_ISUB_8 (0x17a80 >> 3)
#define BIFROST_ADD_ISUB_16 (0x17b00 >> 3)
#define BIFROST_ADD_ISUB_32 (0x17ac0 >> 3)
struct bifrost_add_2src {
unsigned src0 : 3;
unsigned src1 : 3;