fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-25 01:48:18 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
178064 commits 66 branches 936 tags 997 MiB
Commit graph

164870 commits

Author SHA1 Message Date
Roman Stratiienko
8f513813b1 u_gralloc: Add a function that returns gralloc type 
This is needed by some drivers to reject the fallback gralloc.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
 2023-09-21 10:50:34 +00:00
Roman Stratiienko
d923d6234d Revert "util: Add NONNULL macro" 
We agreed in [1] not to use it since it has little value,
but making a code less readable.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256

This reverts commit 21dcde096f.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
 2023-09-21 10:50:34 +00:00
Roman Stratiienko
3b6f14c4d3 u_gralloc: Remove usage of NONNULL macro 
We agreed in [1] not to use it since it has little value,
but making a code less readable.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
 2023-09-21 10:50:34 +00:00
Roman Stratiienko
28b21fae6e u_gralloc: Remove inline modifiers from the functions 
Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
 2023-09-21 10:50:34 +00:00
Georg Lehmann
336ec2a4b4 aco: simplify masked swizzle dpp selection by removing or_mask first 
and_mask and xor_mask alone can represent all patterns without or_mask

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25115>
 2023-09-21 10:07:27 +00:00
Karol Herbst
33ca3a999c rusticl/kernel: skip adding global id offsets if not used 
This allows us to shrink the kernel input buffer quite significantly as
the offset is a vec aligned size_t3 value.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>
 2023-09-21 07:58:34 +00:00
Karol Herbst
a9f408bd52 rusticl/mesa: fix set_constant_buffer when passing an empty buffer 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>
 2023-09-21 07:58:34 +00:00
Jordan Justen
f1b9b7f955 intel/fs: Update SSBO & shared uniform block loads for Xe2 
Note: lower_lsc_block_logical_send() most likely stills needs some
related updates.

Ref: a358b97c58 ("intel/fs: optimize uniform SSBO & shared loads")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
9fb2b12c99 intel/compiler: Update RT stack_id access for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
d371565d34 intel/compiler: Update ray-tracing intrinsic lowering for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
3d744a6890 intel/compiler: Update lower_trace_ray_logical_send() for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
9e43fa09a6 intel/compiler: Update emit_rt_lsc_fence() for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
9846dd798b intel/compiler: Update opt_split_sends() for Xe2 reg size 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:04 -07:00
Jordan Justen
727ab2c11d intel/compiler/fs: Support Xe2 reg size in assign_curb_setup 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
cef4d53daf intel/xe2+: Round up size to reg_unit() in fs_reg_alloc::alloc_spill_reg(). 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
fe3d90aedf intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
791d040104 intel/fs/xe2+: Fix execution width of SHADER_OPCODE_GET_BUFFER_SIZE for SIMD16 EU. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
ac4f598577 intel/fs/xe2+: Update regioning lowering offset alignment checks for Xe2 regs. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
37e280f28a intel/fs: Lower unsupported regioning with non-trivial 2D regions on FIXED_GRFs. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Caio Oliveira
dd632bf527 intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Caio Oliveira
8944ac7d6c intel/fs/xe2+: Update BS payload setup for Xe2 reg size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
14e1b9ee69 intel/fs/xe2+: Update TES payload setup for Xe2 reg size. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
4b3243104c intel/fs/xe2+: Update TCS payload setup for Xe2 reg size. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
6195eac210 intel/fs/xe2+: Update GS payload setup for Xe2 reg size. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Caio Oliveira
28744c8954 intel/compiler/xe2: Account for reg_unit() in TES intrinsics 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Caio Oliveira
9859f5b4d2 intel/compiler/xe2: Account for reg_unit() in TCS intrinsics 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
610daa3166 intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Ian Romanick
c9f2857546 intel/compiler/xe2: TXD is lowered to SIMD16 in SIMD32 mode 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Ian Romanick
ef817650c9 intel/compiler/xe2: Use SIMD16 for nir_intrinsic_image_size 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Ian Romanick
0b23df3951 intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size 
[ Francisco Jerez: Simplify. ]

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Rohan Garg
42b90f05f6 intel/compiler: Adjust barrier emission for Xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
8b1dc77521 intel/fs/xe2+: Scale BRW_MAX_MSG_LENGTH by native register size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Rohan Garg
4de065f6a2 intel/compiler: Adjust fence message lengths for new register width on Xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Rohan Garg
e1289d6135 intel/compiler: Adjust CS payload registers for new register width on Xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
150b3e87c8 intel/fs/xe2+: Round up fs_builder::vgrf() size calculation to HW register unit. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
24dcc3269b intel/fs/xe2+: Update encoding of FB write message payload. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
a573531785 intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
17ef5e7ead intel/fs/xe2+: Allow increased SIMD width for various get_fpu_lowered_simd_width() restrictions. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
6423cb9bfa intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
00b614a5a7 intel/fs/xe2+: Scale MAX_SAMPLER_MESSAGE_SIZE by native register size. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
421d43fe62 intel/fs/xe2+: Fixes for increased accumulator register width. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
80e9031b44 intel/fs/xe2+: Fix grf_count in post-RA scheduling for updated register file size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
571ddf8516 intel/fs/xe2+: Fix payload node live range calculations for change in register size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
2b7419d090 intel/fs: Fix signedness of payload_node_count argument of calculate_payload_ranges(). 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
abf8111560 intel/eu/xe2+: Fix encoding of various message descriptors for change in register size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
6d39b3d6ae intel/fs/ra/xe2: Scale up register allocation granularity by 2x on Xe2+ platforms. 
v2: Fix spill register allocation.  Switch to brw_reg::nr
    representation in fake 256b units.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
bd98df5d8e intel/compiler: Make MAX_VGRF_SIZE macro depend on devinfo and update it for Xe2. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
a7d521e556 intel/vec4/ra: Define REG_CLASS_COUNT constant specifying the number of register classes. 
Rework:
 * Jordan: 16=>20 following d33aff783d ("intel/fs: add support for
   sparse accesses")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:35 -07:00
Francisco Jerez
5d87f41a54 intel/fs/ra: Define REG_CLASS_COUNT constant specifying the number of register classes. 
Rework:
 * Jordan: 16=>20 following d33aff783d ("intel/fs: add support for
   sparse accesses")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:35 -07:00
Connor Abbott
c93bcb32fe amd: Use inverse ballot intrinsic if available 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>
 2023-09-20 14:41:18 +00:00