Commit graph

56805 commits

Author SHA1 Message Date
Chia-I Wu
8e7987cc49 ilo: add support for TBOs on GEN6
This hunk was missing in the last commit.
2013-05-27 12:30:42 +08:00
Chia-I Wu
11c9aaf30a ilo: advertise supports for pure integer formats
For pure integer formats, no filtering nor blending is needed.
2013-05-27 11:02:57 +08:00
Chia-I Wu
fb40aca879 ilo: add support for texture buffer objects
Take care of sampler views that have buffers as the underlying resources.
Update caps related to TBOs.
2013-05-27 11:02:57 +08:00
Chia-I Wu
441aa9326a tgsi: add buffer texture to tgsi_util_get_texture_coord_dim()
TGSI_TEXTURE_BUFFER is one-dimensional.  Assert that exec_tex() is never
called with TGSI_TEXTURE_BUFFER.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-05-27 11:02:06 +08:00
Vadim Girlin
63d09a0cb7 r600g/sb: improve handling of KILL instructions
This patch improves handling of unconditional KILL instructions inside
the conditional blocks, uncovering more opportunities for if-conversion.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-27 01:45:07 +04:00
Vadim Girlin
880f435a7e r600g/sb: fix peephole optimization for PRED_SETE
Fixes incorrect condition that prevented optimization for
PRED_SETE/PRED_SETE_INT.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-27 01:45:07 +04:00
Vadim Girlin
ff2a611699 r600g/sb: fix scheduling of PRED_SET instructions
PRED_SET instructions that update exec mask should be scheduled immediately
prior to the "if-then-else" block, because any instruction that is
inserted after alu clause with PRED_SET and before conditional block is
also conditionally executed by hw (exec mask is already updated at that
moment).

Propbably it's better to make PRED_SET a part of conditional
"if-then-else" block in the IR to handle this more cleanly,
but for now this temporary solution should prevent the problem.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-27 01:45:07 +04:00
Vadim Girlin
44a117ab9a r600g/sb: fix handling of preloaded inputs for compute shaders
For compute shaders we need to let the backend know that
GPRs 0 and 1 are preloaded with some compute-specific input
values, otherwise any use of these regs without previous
definition is considered as undefined value and usually
is simply replaced with 0.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-25 22:56:53 +04:00
Brian Paul
fd9fe4470b xlib: add null ctx check in glXDestroyContext()
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934
NOTE: This is a candidate for the stable branches.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-24 16:35:25 -06:00
Brian Paul
fd29e4acda st/glx: add null ctx check in glXDestroyContext()
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934
NOTE: This is a candidate for the stable branches.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-24 16:35:25 -06:00
Brian Paul
db4580cbdf st/mesa: add switch cases for new IR enums to silence warnings 2013-05-24 16:35:25 -06:00
Brian Paul
820de34ceb st/glx/xlib: assorted whitespace, comment fixes 2013-05-24 16:35:24 -06:00
Vadim Girlin
8e41ced4b3 r600g/sb: fix incorrect assert
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-24 21:00:54 +04:00
Vadim Girlin
e9aa46e665 r600g/sb: relax some restrictions for FETCH instructions
This allows GVN rewrite pass to propagate non-const (register)
values to FETCH source operands, helping to eliminate unnecessary
copies in some cases.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-24 21:00:54 +04:00
Vadim Girlin
5a68a29706 r600g/sb: relax register allocation for compute shaders
We have to assume that all GPRs in compute shader can be indirectly
addressed because LLVM backend doesn't provide any indirect array info.
That's why for compute shaders GPR array is created that covers all used
GPRs (0..r600_bytecode::ngpr-1), but this seriously restricts register
allocation in sb.

This patch checks for actual use of indirect access in the shader and
if it's not used then GPR array is not created, so that regalloc is not
unnecessarily restricted.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-24 21:00:54 +04:00
Vadim Girlin
0b5b3f8816 r600g/sb: fix gpr array handling for compute shaders
Fixes segfault with bfgminer and R600_DEBUG=sbcl.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-24 16:45:58 +04:00
Vadim Girlin
d1e0dc6275 r600g/sb: fix buffer overflow in sb_ostream
Fixes segfault during bytecode dump with bfgminer kernel

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-05-24 16:40:58 +04:00
Tom Stellard
b1797c3a38 r600g/compute: Use common transfer_{map,unmap} functions for global resources
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2013-05-23 14:52:34 -07:00
Tom Stellard
65d67bcc4b r600g/compute: Use common transfer_{map,unmap} functions for kernel inputs
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2013-05-23 14:52:34 -07:00
Kenneth Graunke
062317d667 i965: Go back to using the kernel SOL reset feature.
It turns out the MI_LOAD_REGISTER_IMM approach doesn't work on Haswell,
and regressed essentially all the transform feedback Piglit tests.

This morally reverts eaa6fbe6d5.  However,
the code is still simpler than it was.  On BeginTransformFeedback, we
simply flush the batch and set the SOL reset flag so that the next batch
will start with zeroed offsets.  There's still no software counting.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64887
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-05-23 13:32:02 -07:00
Rob Clark
95670bdee2 freedreno: scissor fix
Don't assume the state-tracker will set the scissor after the
framebuffer state is changed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-05-23 14:35:21 -04:00
Rob Clark
97fa811d14 freedreno: implement pipe->resource_copy_region()
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-05-23 14:35:21 -04:00
Kenneth Graunke
3ddfccb303 glsl linker: compare interface blocks during interstage linking
Verify that interface blocks match when linking separate shader
stages into a program.

Fixes piglit glsl-1.50 tests:
* linker/interface-blocks-vs-fs-member-count-mismatch.shader_test
* linker/interface-blocks-vs-fs-member-order-mismatch.shader_test

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2013-05-23 09:37:12 -07:00
Jordan Justen
4a0bcd90cf glsl linker: compare interface blocks during intrastage linking
Verify that interface blocks match when combining compilation
units at the same stage. (For example, when merging all vertex
shaders.)

Fixes piglit glsl-1.50 test:
* linker/interface-blocks-multiple-vs-member-count-mismatch.shader_test

v5 (Ken): Rename to link_interface_blocks.cpp and drop the separate .h
file for consistency with other linker code.  Remove "ok" variable.
Fold cross_validate_interface_blocks into its caller.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:12 -07:00
Jordan Justen
d6863acb9f glsl linker: support arrays of interface block instances
With this change we now support interface block arrays.
For example, cases like this:

out block_name {
    float f;
} block_instance[2];

This allows Mesa to pass the piglit glsl-1.50 test:
* execution/interface-blocks-complex-vs-fs.shader_test

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:12 -07:00
Jordan Justen
c30ca431ba glsl link_varyings: link interface blocks using the block name
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:12 -07:00
Jordan Justen
5ebf547312 glsl linker: remove interface block instance names
Convert interface blocks with instance names into flat
interface blocks without an instance name.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:12 -07:00
Jordan Justen
b24eeb078f glsl ast_to_hir: support in/out for interface blocks
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:12 -07:00
Jordan Justen
cb29a7095f glsl ast_to_hir: reject row/column_major for in/out interface blocks
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:12 -07:00
Jordan Justen
c00387497d glsl ast_to_hir: move uniform block symbols to interface blocks namespace
Uniform/interface blocks are a separate namespace from types.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:12 -07:00
Jordan Justen
3919c19468 glsl_symbol_table: add interface block namespaces
For interface blocks, there are three separate namespaces for
uniform, input and output blocks.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:12 -07:00
Jordan Justen
9368604d99 glsl parser: allow in & out for interface block members
Previously uniform blocks allowed for the 'uniform' keyword
to be used with members of a uniform blocks. With interface
blocks 'in' can be used on 'in' interface block members and
'out' can be used on 'out' interface block members.

The basic_interface_block rule will verify that the same
qualifier type is used with the block and each member.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:11 -07:00
Jordan Justen
067cc08d6a glsl ast_to_hir: reject interpolation qualifiers for uniform blocks
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:11 -07:00
Jordan Justen
4410eba598 glsl parser: handle interface block member qualifier
An interface block member may specify the type:
in {
    in vec4 in_var_with_qualifier;
};

When specified with the member, it must match the same
type as interface block type.

It can also omit the qualifier:
uniform {
    vec4 uniform_var_without_qualifier;
};

When the type is not specified with the member,
it will adopt the same type as the interface block.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:11 -07:00
Jordan Justen
4369acff5e glsl parser: on desktop GL require GLSL 150 for instance names
Interface blocks in GLSL 150 allow an instance name to be used.

v2:
 * use state->check_version

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:11 -07:00
Jordan Justen
d36cb3617c glsl parser: reject VS+in & FS+out interface blocks
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:11 -07:00
Jordan Justen
6d3d974e37 glsl: parse in/out types for interface blocks
Previously only 'uniform' was allowed for uniform blocks.

Now, in/out can be parsed, but it will only be allowed for
GLSL >= 150.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:11 -07:00
Jordan Justen
744c270406 glsl parser: rename uniform block to interface block
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:11 -07:00
Jordan Justen
c9f58544be glsl: rename ast_uniform_block to ast_interface_block
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-23 09:37:11 -07:00
Chris Forbes
7bfb4bea65 i965: Enable guardband clipping on Gen4/5.
Enables guardband clipping when the viewport covers the entire render
target.

No piglit regressions on Ironlake.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-05-24 08:00:47 +12:00
Chris Forbes
a3d8e7c57c ARB_fp: accept duplicate precision options
Relaxes the validation of

   OPTION ARB_precision_hint_{nicest,fastest};

to allow duplicate options. The spec says that both /nicest/ and
/fastest/ cannot be specified together, but could be interpreted
either way for respecification of the same option.

Other drivers (NVIDIA etc) accept this, and at least one Unity3D game
expects it to succeed (Kerbal Space Program).

V2: Add spec quote.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-24 07:50:51 +12:00
Vinson Lee
e3eeb72f24 ilo: Initialize need_flush in draw_vbo.
need_flush was uninitialized if hw3d->new_batch was true.

Fixes "Uninitialized scalar variable" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2013-05-23 15:31:42 +08:00
Vinson Lee
36e2c7cc1a radeon: Initialize variables in radeon_llvm_context_init.
'type' was not fully initialized when calling lp_build_context_init.

Fixes "Uninitialized scalar variable" defect reported by Coverity.

NOTE: This is a candidate for the stable branches.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-05-22 23:06:23 -07:00
Eric Anholt
cf37e12024 intel: Count fragments in our blitter-based glBitmap() path.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59440
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-22 14:35:44 -07:00
Eric Anholt
0af614727a i965: Shut up more compiler warnings from vector insert/extract changes.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-22 14:35:25 -07:00
Roland Scheidegger
2b291eaa90 softpipe: change TEX_TILE_SIZE and NUM_TEX_TILE_ENTRIES
Initially we had NUM_TEX_TILE_ENTRIES of 50, however this was using too much
memory (mostly because the tile cache is operating on fixed max current
sampler views which could be fixed but that's another topic). So it was
decreased to 4. However this is a ridiculously low number which can't
actually really work (the number of tiles needed for as little as
a single quad with linear_mipmap_linear is 2 to 8 for a 2d texture, and
4 to 16 for a 3d texture), as it just about guarantees there will be
cache thrashing sometimes (just about always for 3d textures in fact, since
while there are 4 entries the cache is direct mapped).
So increase that number to 16 (which is still on the low side for direct
mapped cache though I guess using something like 4-way associativity would
be more effective than increasing this further) which has at least some good
chance to avoid thrashing. Since we don't want to increase memory requirements
however in turn decrease the tile size accordingly from 64 to 32 (as a bonus
point this also decreases the cost of texture thrashing which might still
happen sometimes).
I've seen performance improvement in the order of factor ~200 (specifically,
drawing the first frame from the replay from bug 41787 needs "only" ~10s
instead of ~30min, meaning I can actually compare the output with other
drivers...) with this.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Roland Scheidegger
2f567fb7b5 softpipe: disambiguate TILE_SIZE / TEX_TILE_SIZE
These can be different (just like NUM_TEX_TILE_ENTRIES / NUM_ENTRIES),
though currently they aren't.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Roland Scheidegger
80e2cc0f97 llvmpipe: disable simple_shader optimization
This optimization disabled mask checks if the shader is simple enough.
While this should work correctly, the problem is that it can hide real issues
because shaders in practice are usually complex enough (8 instructions or 1
texture is already enough) so this doesn't get used, whereas dumbed-down
tests which should hit all the same code paths suddenly do something quite
different. This was the reason that bug 41787 could not be easily tracked as
stencil test not working correctly (piglit would in fact have failed some
tests without that optimization).
So disable it for now, it's unclear if it's much of a win in any case.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Roland Scheidegger
e108716429 llvmpipe: fix early depth test / late depth write stencil issues
We actually did early depth/stencil test and late depth/stencil write even
when the shader could kill the fragment (alpha test or discard). Since it
matters for the new stencil value if the fragment is killed by depth/stencil
test or by the shader (in which case it will not reach the depth/stencil
test) this simply cannot work (we also would possibly skip writing the new
stencil value due to mask checks but this is a secondary issue).
So use late depth test / late depth write instead in this case.
(No piglit changes as it doesn't seem to hit such bogus early depth test
/ late depth write path.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00
Roland Scheidegger
82d7733b52 llvmpipe: fix issue with not writing new stencil values
We did mask checks between depth/stencil testing and depth/stencil write.
This meant that if the depth/stencil test killed off all fragments we never
actually wrote the new stencil value. This issue affected all early/late
test/write combinations.
So move the mask check after depth/stencil write (for early depth test,
could do the same for late depth test but might not be worth it at that
point so just skip it there).
This addresses https://bugs.freedesktop.org/show_bug.cgi?id=41787.
Piglit does not hit this issue because of the simple_shader optimization
in generate_fs_loop() which means we're skipping the mask checks.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-22 22:57:27 +02:00