Commit graph

181311 commits

Author SHA1 Message Date
Rohan Garg
8cfae77439 anv: enable VK_EXT_depth_range_unrestricted
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26426>
2023-12-01 13:23:54 +00:00
Rohan Garg
80cafa3571 anv: ensure that we clamp only when EXT_depth_range_unrestricted is not enabled
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26426>
2023-12-01 13:23:54 +00:00
Rohan Garg
2e72917923 blorp: set min/max viewport depths to -FLT_MAX/FLT_MAX when EXT_depth_range_unrestricted is enabled
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26426>
2023-12-01 13:23:54 +00:00
Samuel Pitoiset
ced313eec8 radv: make sure to prefetch the compute shader for DGC
It was never prefetched. These two helpers should be refactored with
radv_dispatch() though.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
2023-12-01 12:25:46 +00:00
Samuel Pitoiset
ab6cf1592f radv: fix bogus interaction between DGC and RT with descriptor bindings
pipeline_is_dirty was never TRUE because it's emitted in the before
helper. This might fix bad interactions between DGC and RT because
they both use compute shaders and descriptor bindings need to be
re-emitted.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
2023-12-01 12:25:46 +00:00
Frank Binns
b6f3b55b88 pvr: Add powervr winsys implementation
Co-authored-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Co-authored-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Co-authored-by: Sarah Walker <sarah.walker@imgtec.com>
Co-authored-by: Matt Coster <matt.coster@imgtec.com>
Co-authored-by: Donald Robson <donald.robson@imgtec.com>
Co-authored-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15507>
2023-12-01 10:41:24 +00:00
Sarah Walker
be82fe7ab9 pvr: Add command stream and static context state layout to rogue_kmd_stream.xml
Co-authored-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15507>
2023-12-01 10:41:24 +00:00
Sarah Walker
90916c955b pvr: csbgen: Add dummy implementation of stream type
This is enough of an implementation to allow stream layout to be added to
rogue_kmd_stream.xml.

Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15507>
2023-12-01 10:41:24 +00:00
Frank Binns
d9132b63d9 include/drm-uapi: add pvr_drm.h
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15507>
2023-12-01 10:41:24 +00:00
Erik Faye-Lund
3a46181fe0 zink: do not handle PIPE_SWIZZLE_NONE
This is not a valid value for texture-views, whic is what we currently
use it for... And it's not the same as an identity swizzle anyway, in
the case we'd want to use it for something else in the future.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26192>
2023-12-01 07:53:58 +00:00
Erik Faye-Lund
d7e067823b d3d12: do not handle PIPE_SWIZZLE_NONE from sampler-view
This shouldn't be possible, so not need to handle it.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26192>
2023-12-01 07:53:58 +00:00
Erik Faye-Lund
a5970c1a01 panfrost: do not handle NONE-swizzle
Neigher PIPE_SWIZZLE_NONE nor PIPE_SWIZZLE_MAX are legal here, so let's
not even try to handle it. If we ever get either here, we're triggering
a bug anyway.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26192>
2023-12-01 07:53:58 +00:00
Erik Faye-Lund
e233eee492 lavapipe: do not use NONE-swizzle
The NONE-swizzle isn't supported for texture views in LLVMpipe, because
it's not meant for this purpose in the first place.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26192>
2023-12-01 07:53:58 +00:00
Erik Faye-Lund
1fbec9f532 util/format: document NONE swizzle
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26192>
2023-12-01 07:53:58 +00:00
ratatouillegamer
5f7aa0e012 hasvk: Enable hasvk override Vulkan API Version for Brawlhalla
Brawlhalla runs good with DXVK 2.0+, it can be enable as default
avoiding to use OpenGL Brawlhalla renderer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26433>
2023-12-01 07:18:10 +00:00
ratatouillegamer
9de6928746 hasvk: Add Vulkan API version override
This allows to use a driconf to override the API version and expose Vulkan 1.3.
That can be used in conjunction with certain games like for example Brawlhalla
which benefits from some DXVK +2.0 features.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26433>
2023-12-01 07:18:10 +00:00
Gert Wollny
c13de0509c r600/sfn: Don't try to re-use iterators when the set is made empty
It seems with libc++ the iterators are invalidated when the set
is emptied during iterating over it.

Fixes: 05fab97 (r600/sfn: Don't try to re-use the iterator when uses is updated)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7931

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26420>
2023-12-01 06:37:30 +00:00
Qiang Yu
b16017d080 nir: fix load layer id system_values_read info gather
Otherwise radeons+ACO compilation fail.

Fixes: 32ee6376ad ("nir: add lowering from FS LAYER input to LAYER_ID sysval")
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26422>
2023-12-01 03:17:57 +00:00
Rohan Garg
a499be0ee3 intel/genxml: Update IDD for new fields
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Rohan Garg
c916038b89 intel/genxml: Update COMPUTE_WALKER_BODY for xe2
Reworks:
 * Caio: Change patch to only add COMPUTE_WALKER_BODY and
   EXECUTE_INDIRECT_DISPATCH (that uses it).

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Rohan Garg
cc2dce82bc intel: Set a preferred SLM size for LNL
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Jordan Justen
16483cd4bc iris: xe2 doesn't have INTERFACE_DESCRIPTOR_DATA::BarrierEnable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Rohan Garg
ef1c1ca821 intel/genxml: Add the preferred slm size enum for xe2
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Jordan Justen
1e9972991c anv, iris: Update INTERFACE_DESCRIPTOR_DATA programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Jordan Justen
bdb9c70f84 intel/genxml: Update INTERFACE_DESCRIPTOR_DATA for xe2
Reworks:
 * Caio: Remove "Mask Stack Exception Enable", not present in BSpec.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Jordan Justen
d95bbf35c9 anv: Set COMPUTE_WALKER Message SIMD field
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Jordan Justen
59dc9b1df6 iris: Set COMPUTE_WALKER Message SIMD field
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Jordan Justen
aafdf59dfe intel/genxml: Update COMPUTE_WALKER for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Jordan Justen
064bdecb36 intel/compiler: Define XE2 compiler enum
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
2023-12-01 02:36:12 +00:00
Tatsuyuki Ishi
eb0419a1aa radv: Remove aspect mask "expansion" for copy_image.
The Vulkan spec says multi-planar images can only be copied on a
per-plane basis. The COLOR_BIT to "all planes" expansion applies to
image memory barriers which is completely unrelated.

Remove the expansion logic to simplify the code. Add assertions to
clearly describe the invariant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26364>
2023-12-01 01:52:04 +00:00
Marek Olšák
7ffb65f935 ac: add an IB parser that gathers context rolls
This is an important performance bottleneck analysis tool.

Try it with radeonsi: AMD_ROLLS=filename app

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
2023-12-01 01:15:55 +00:00
Marek Olšák
f0cb8852a4 ac: move the IB parsers into ac_parse_ib.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
2023-12-01 01:15:55 +00:00
Marek Olšák
c5fe2780e6 ac: rename ac_parse_ib.c -> ac_ib_parser.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
2023-12-01 01:15:55 +00:00
Peyton Lee
95c933c8b7 winsys, amdgpu, drm: add VPE submission handle
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
2023-12-01 00:23:38 +00:00
Peyton Lee
a212e9bdbf amd, radeonsi: supports post processing entrypoint
create a new decoder for handling post processing

Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
2023-12-01 00:23:38 +00:00
Peyton Lee
ed176e2c71 amd, radeonsi: add si_vpe.c with helper functions of VPE lib
Signed-off-by: Peyton Lee <peytolee@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
2023-12-01 00:23:38 +00:00
Peyton Lee
3ec397819e amd: add new hardware ip for vpe
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
2023-12-01 00:23:38 +00:00
Peyton Lee
17c20ceda7 amd,radeonsi: add libvpe
Signed-off-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Alan Liu <haoping.liu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
2023-12-01 00:23:38 +00:00
Peyton Lee
6b441ef6ab frontends, va: add new parameters of post processor
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
2023-12-01 00:23:38 +00:00
Jesse Natalie
be05c9458a microsoft/clc: Fix image lowering pass to only erase variables at the end
Otherwise, if a variable has multiple derefs in a shader, we'll crash
trying to remove it a second time. No idea how that can happen though,
seems derefs got sunk by opt_dead_cf.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26435>
2023-11-30 23:32:08 +00:00
Lynne
aff59c63eb radv: change queue family order in radv_get_physical_device_queue_family_properties
Fixes: 748b7f80ef ("radv: Move sparse binding into a dedicated queue.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26428>
2023-11-30 22:45:49 +00:00
José Roberto de Souza
42dd48e933 anv: Fix vm bind of DRM_XE_VM_BIND_FLAG_NULL
In this case bo is NULL so application was crashing when it was trying
to get the alloc_flags of bo to get the intel_device_info_pat_entry.

Fixes: 1a0d3504d5 ("anv: Fill PAT fields in Xe KMD gem_create and vm_bind uAPIs")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26430>
2023-11-30 22:22:41 +00:00
Rhys Perry
5bc27e80c9 ac/nir: fix 32-bit offset global access optimization
Since 38cff03e58 ("radv: use nir_lower_conv64"), u2u64(a) is replaced
with pack_64_2x32_split(a, 0).

fossil-db (navi31):
Totals from 1203 (1.52% of 79330) affected shaders:
MaxWaves: 33685 -> 33813 (+0.38%)
Instrs: 1407031 -> 1374689 (-2.30%); split: -2.32%, +0.02%
CodeSize: 7088652 -> 6917320 (-2.42%); split: -2.43%, +0.01%
VGPRs: 69276 -> 68988 (-0.42%); split: -0.43%, +0.02%
SpillSGPRs: 982 -> 977 (-0.51%); split: -0.92%, +0.41%
Latency: 12536511 -> 12451605 (-0.68%); split: -0.94%, +0.27%
InvThroughput: 2456803 -> 2431241 (-1.04%); split: -1.09%, +0.05%
VClause: 27624 -> 27832 (+0.75%); split: -1.88%, +2.64%
SClause: 31757 -> 32702 (+2.98%); split: -0.53%, +3.51%
Copies: 90923 -> 91238 (+0.35%); split: -1.47%, +1.81%
Branches: 25127 -> 25128 (+0.00%); split: -0.00%, +0.01%
PreSGPRs: 46025 -> 46068 (+0.09%); split: -0.53%, +0.62%
PreVGPRs: 53944 -> 53488 (-0.85%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
2023-11-30 21:50:21 +00:00
Rhys Perry
10ba06960f ac/nir: ignore 8/16-bit global access offset
This was found by inspection, I'm not sure it can even happen.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
2023-11-30 21:50:21 +00:00
Caio Oliveira
bbb12dbbf9 intel/compiler: Add a few tests to opt_predicated_break
v2 (idr): Fix expectations BottomBreakWithContinue. opt_predicated_break
will remove the IF and make the CONTINUE predicated.

v3 (idr): Temporarily disable the one test that fails.

v4 (idr): Free strings allocated by open_memstream. Fixes gitlab CI
failures in debian-testing-asan.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
2023-11-30 20:58:05 +00:00
Caio Oliveira
0b072c5351 intel/compiler: Sort lists of succs and preds in CFG dump output
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
2023-11-30 20:58:05 +00:00
Caio Oliveira
47c5656f0e intel/compiler: Allow dumping CFG to a specific FILE*
Add optional argument for both cfg and block dump() function to pass
a FILE*.  Default behavior remains dumping to stderr.

v2 (idr): Don't add the new test framework in this commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
2023-11-30 20:58:05 +00:00
Caio Oliveira
21cf9323f0 intel/compiler: Add a few more helpers to fs_builder
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
2023-11-30 20:58:05 +00:00
Ian Romanick
c0ecc0d70b intel/compiler: Don't promote CFG link types when removing a block
Imagine 3 blocks A, B, and C. A has a physical link to B, and B has a
logical link to C. Previous to this commit, if B were removed, A would
get a logical link to C. This is not correct.

This was specifically observed to occur when block A was a DO block and
B was the WHILE block. The DO block would have two logical successors,
and that is completely invalid.

v2: Assert that the links from A-to-B and B-back-to-A are the same
kind. Suggested by Caio.

v3: Assume the successor and predecessor lists are well formed. Use this
to simplify the logic. Suggested by Caio. Add checks to cfg_t::validate
to ensure the lists are well formed.

v4: Remove (now unused) bblock_link_invalid. Suggested by Curro.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
2023-11-30 20:58:05 +00:00
Ian Romanick
77c0c1ce54 intel/compiler: Don't create extra CFG links when deleting a block
The previous is_successor_of and is_predecessor_of checks prevented
creating a physical link when a logical link already existed. However, a
logical link could be added when a physical link already existed. This
change causes an existing physical link to be "promoted" to a logical
link.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
2023-11-30 20:58:05 +00:00