Commit graph

57709 commits

Author SHA1 Message Date
Chia-I Wu
cde49c71a3 ilo: add support for TEX2/TXB2/TXL2 in fs
They were already supported, just being rejected in the TGSI translator.
2013-06-07 15:37:35 +08:00
Vinson Lee
f8df73f41c glsl linker: Initialize member variable interface_namespace.
Fixes "Uninitialized pointer field" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-06 22:55:24 -07:00
Chia-I Wu
7142da6dd1 ilo: use slab allocator for transfers
Slab allocator is perfect for transfer.  Improved OpenArena performance by 1%
with several casual runs.
2013-06-07 13:23:43 +08:00
Chia-I Wu
09f62a13fc ilo: clean up states upon context destroy
We need to unreference resources that we referenced.
2013-06-07 11:28:21 +08:00
Chia-I Wu
7cbf0a410e ilo: unmap cp bo before destroying it
The BOs are mapped in their entire life times for the chipsets we support so
do not forget to unmap it.
2013-06-07 11:28:20 +08:00
Chia-I Wu
27804b2fc7 ilo: enable bo reuse
This magical line of code must have got lost at some point in the history...
2013-06-07 11:28:20 +08:00
Chia-I Wu
20d23b2275 ilo: construct 3DSTATE_SF in create_rasterizer_state()
Add ilo_rasterizer_sf and initialize it in create_rasterizer_state().
2013-06-07 11:13:16 +08:00
Chia-I Wu
3c2fea206f ilo: construct 3DSTATE_CLIP in create_rasterizer_state()
Add ilo_rasterizer_clip and initialize it in create_rasterizer_state().
2013-06-07 11:13:16 +08:00
Chia-I Wu
4006f4ce26 ilo: use emit_SURFACE_STATE() for render targets
Introduce ilo_surface_cso and initialize it in create_surface().  With the
change, we can emit SURFACE_STATE directly from the CSO and remove
emit_surf_SURFACE_STATE().  We do not deal with depth/stencil surfaces yet.
2013-06-07 11:13:16 +08:00
Chia-I Wu
5354dc7428 ilo: use emit_SURFACE_STATE() for constant buffers
Introduce ilo_cbuf_cso and initialize it in set_constant_buffer().  As
ilo_view_surface is embedded in ilo_cbuf_cso, switch to emit_SURFACE_STATE()
for constant buffers and remove emit_cbuf_SURFACE_STATE().
2013-06-07 11:13:16 +08:00
Chia-I Wu
2d82885d3c ilo: add emit_SURFACE_STATE() for sampler views
Introduce ilo_view_cso and initialize it in create_sampler_view().  Add
emit_SURFACE_STATE() to GPE, which can emit SURFACE_STATE from
ilo_view_surface.
2013-06-07 11:13:16 +08:00
Chia-I Wu
39e947569e ilo: add ilo_view_surface for SURFACE_STATE
Define struct ilo_view_surface for SURFACE_STATE construction and emission.
2013-06-07 11:13:15 +08:00
Courtney Goeltzenleuchter
c6983ea035 ilo: convert generic depth-stencil-alpha pipe state to ilo pipe state
Moving the work to create time reduces the work at emit time.
Saves time overall as create work is only done once.
Fix compiler warning in gen7_pipeline_sol.

[olv: remember pipe_alpha_state instead of pipe_depth_stencil_alpha_state in
      ilo_dsa_state]
2013-06-07 11:13:15 +08:00
Chia-I Wu
70e78211d6 ilo: introduce vertex element CSO
Introduce ilo_ve_cso and initialize it in create_vertex_elements_state().
This commit goes a step further by setting up mappings from HW VB to PIPE VB,
which we failed to do previously.  That allows us to support instanced
rendering.
2013-06-07 11:13:15 +08:00
Chia-I Wu
d4fa98db0c ilo: simplify emit_3DSTATE_DEPTH_BUFFER()
Remove hiz and dsa from the parameters.  We would know whether HiZ buffer
exists from ilo_texture once it is supported.  DSA state should not affect
3DSTATE_DEPTH_BUFFER.
2013-06-07 11:13:15 +08:00
Chia-I Wu
eea1be2072 ilo: introduce blend CSO
Introduce ilo_blend_cso and initialize it in create_blend_state().  This saves
us from having to construct hardware blend states in draw_vbo().
2013-06-07 11:13:15 +08:00
Chia-I Wu
b3c9e2161f ilo: introduce sampler CSO
Introduce ilo_sampler_cso and initialize it in create_sampler_state().  This
saves us from having to perform CPU-intensive calculations to construct
hardware sampler states in draw_vbo().
2013-06-07 11:13:15 +08:00
Chia-I Wu
99725d2f8a ilo: construct SCISSOR_RECT in set_scissor_states()
This allows us to memcpy() the state in draw_vbo().  Add ilo_init_states() and
ilo_cleanup_states() that are called when contexts are created and destroyed
respectively, and properly set the initial scissor state in ilo_init_states().
2013-06-07 11:13:15 +08:00
Chia-I Wu
e51806ee7a ilo: introduce viewport CSO
Introduce ilo_viewport_cso and initialize it in set_viewport_states().  This
saves us from having to perform CPU-intensive calculations to construct
hardware viewport states in draw_vbo().
2013-06-07 11:13:15 +08:00
Chia-I Wu
4228cf3746 ilo: switch to ilo states for shaders and resources
Define and use

 struct ilo_sampler_state;
 struct ilo_view_state;
 struct ilo_cbuf_state;
 struct ilo_resource_state;
 struct ilo_global_binding;

in ilo_context.
2013-06-07 11:13:15 +08:00
Chia-I Wu
94212915ee ilo: switch to ilo states for CC stage
Define and use

 struct ilo_dsa_state;
 struct ilo_blend_state;
 struct ilo_fb_state;

in ilo_context.
2013-06-07 11:13:15 +08:00
Chia-I Wu
29b938d9f4 ilo: switch to ilo states for WM stage
Define and use

 struct ilo_rasterizer_state;

in ilo_context.
2013-06-07 11:13:15 +08:00
Chia-I Wu
130364ad1d ilo: switch to ilo states for CLIP and SF stages
Define and use

 struct ilo_viewport_state;
 struct ilo_scissor_state;

in ilo_context.
2013-06-07 11:13:14 +08:00
Chia-I Wu
3bc8289f49 ilo: switch to ilo states for SOL stage
Define and use

 struct ilo_so_state;

in ilo_context.
2013-06-07 11:13:14 +08:00
Chia-I Wu
6b14b392d0 ilo: switch to ilo states for VF stage
Define and use

 struct ilo_vb_state;
 struct ilo_ve_state;
 struct ilo_ib_state;

in ilo_context.
2013-06-07 11:13:14 +08:00
Chia-I Wu
f0af292239 ilo: move hardware limits to ilo_gpe.h 2013-06-07 11:13:14 +08:00
Roland Scheidegger
644b8346fd draw: trivial fix comment typo 2013-06-06 23:51:39 +02:00
Roland Scheidegger
769449b3e8 gallium/tgsi: add missing string for layer semantic
Also report if a shader writes the layer semantic

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-06 23:51:38 +02:00
Roland Scheidegger
d0518c4c69 llvmpipe: bump 3d and cube map limits to 2048 and 8192 respectively
These should just work, required by d3d10. Too large resources will
get thrown out separately anyway.

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-06 23:51:38 +02:00
Eric Anholt
38e77e545d glsl: Fix uniform buffer object counting.
We were counting uniforms located in UBOs against the default uniform
block limit, while not doing any counting against the specific combined
limit.

Note that I couldn't quite find justification for the way I did this, but
I think it's the only sensible thing: The spec talks about components, so
each "float" in a std140 block would count as 1 component and a "vec4"
would count as 4, though they occupy the same amount of space.  Since GPU
limits on uniform buffer loads are surely going to be about the size of
the blocks, I just counted them that way.

Fixes link failures in piglit
arb_uniform_buffer_object/maxuniformblocksize when ported to geometry
shaders on Paul's GS branch, since in that case the max block size is
bigger than the default uniform block component limit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-06-06 14:37:41 -07:00
Eric Anholt
93c8692ce9 glsl: Make a local variable to avoid restating this array lookup.
v2: Convert another instance of the array lookup. (caught by Tapani)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-06-06 14:37:40 -07:00
Kenneth Graunke
757ad82867 intel: Use the CHIPSET macro in the PCI ID tables for the device name.
Putting the human readable device names directly in the PCI ID list
consolidates things in one place.  It also makes it easy to customize
the name on a per-PCI ID basis without a huge code explosion.

Based on a patch by Kristian Høgsberg.

v2: Fix 830M/845G names and #undef CHIPSET (caught by Emit Velikov).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-06 14:28:35 -07:00
Kenneth Graunke
ea92b700df intel: Remove 'misc' parameter from CHIPSET macro in PCI ID tables.
This has never actually been used for anything.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-06 14:28:35 -07:00
Andreas Boll
8bc788ea9e build: Use PACKAGE_VERSION from autoconf
Both variables had the same value.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-06 19:07:22 +02:00
Andreas Boll
c0f7ccc136 build: Unify PACKAGE_VERSION on autotools, scons and Android
This patch unifies mesa's PACKAGE_VERSION on autotools, scons and
Android build systems.

Current behaviour is:
 - Autotools uses 9.2.0 as PACKAGE_VERSION
 - Scons and Android use 9.2-devel as PACKAGE_VERSION

With this patch all three build systems use 9.2.0-devel as
PACKAGE_VERSION.

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-06 19:07:14 +02:00
Jonathan Gray
5bd808a2c7 radeon/winsys: correct RADEON_GEM_WAIT_IDLE use
RADEON_GEM_WAIT_IDLE is declared DRM_IOW but mesa
uses it with drmCommandWriteRead instead of drmCommandWrite
which leads to the ioctl being unmatched and returning an
error on at least OpenBSD.

Problem originally noticed in libdrm by Mark Kettenis.
Dave Airlie pointed out that mesa has the same issue.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
2013-06-06 11:01:18 +02:00
Mike Stroyan
962204961d configure.ac: Build dricommon for gallium swrast
When building dri-swrast, use gallium_check_st to set HAVE_COMMON_DRI.
Commit 07f2dee7 added setting of HAVE_COMMON_DRI in gallium_check_st.
But the dri-swrast case did not use gallium_check_st.
So dri/common was still not built.

v2: set HAVE_COMMON_DRI=yes instead of using gallium_check_st

NOTE: This is a candidate for the 9.1 branch.
      (Depends on 7de78ce5 and 07f2dee)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61821
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
2013-06-06 08:54:07 +02:00
Rodrigo Vivi
ce67fb4715 i965: Adding more reserved PCI IDs for Haswell.
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.

NOTE: This is a candidate for stable branches.

Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-05 10:44:15 -07:00
Rico Schüller
3998cfa933 mesa: remove outdated version lines in comments
Signed-off-by: Brian Paul <brianp@vmware.com>
2013-06-05 08:54:27 -06:00
Richard Sandiford
7bdf1f2f1a gallium: System z support
The main change is to use MCJIT rather than the old JIT, which will never
be supported for System z.  The endianness part is by example since the
patch was tested on a glibc system.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2013-06-05 08:36:24 -06:00
Roland Scheidegger
008fd03600 llvmpipe: improve alignment calculation for fetching/storing pixels
This was always doing per-pixel alignment which isn't necessary, except
for the buffer case (due to the per-element offset). The disabled code
for calculating it was incorrect because it assumed that always the full
block would be fetched, which may not be the case, so fix this up.
The original code failed for instance for r10g10b10a2 the alignment would
have been calculated as 4 (block_width) * 4 (bytes) so 16, but the actual
fetch may have only fetched 2 values at a time, hence only alignment 8 -
it is unclear what exactly would happen in this case (alignment larger
than size to fetch).
So just use the (already calculated) fetch size instead and get alignment
from that which should always work, no matter if fetching 1,2 or 4 pixels.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-05 00:29:47 +02:00
Roland Scheidegger
ffe2a1ca3c llvmpipe: reduce alignment requirement for 1d resources from 4x4 to 4x1
For rendering to buffers, we cannot have any y alignment.
So make sure that tile clear commands only clear up to the fb width/height,
not more (do this for all resources actually as clearing more seems
pointless for other resources too). For the jit fs function, skip execution
of the lower half of the fragment shader for the 4x4 stamp completely,
for depth/stencil only load/store the values from the first row
(replace other row with undef).
For the blend function, also only load half the values from fs output,
replace the rest with undefs so that everything still operates on the
full 4x4 block to keep code the same between 4x1 and 4x4 (except for
load/store of course which also needs to skip (store) or replace these
values with undefs (load))., at the cost of slightly less optimal code
being produced in some cases.
Also reduce 1d and 1d array alignment too, because they can be handled the
same as buffers so don't need to waste memory.

v2: don't try to run special blend code for 4x1, (very) slightly less
complexity if we just use the same code as for 4x4 which may or may not
make it easier to optimize in the future (as we care a lot more about 4x4
performance than 1d).

v2: don't use undef values for unused fs src outputs with llvm 3.1 as it
apparently can trigger a bug in llvm.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-05 00:29:47 +02:00
Roland Scheidegger
ef3e887084 llvmpipe: cleanup of generate_unswizzled_blend
Some parameters were used inconsistently, for instance not using
block_width/block_height/block_size for deferring number of pixels
but rather relying on guesses from the number of fragment shaders etc,
so fix this up (no actual change in behavior since the block size stays
fixed). (Though most of the code would work with different block_height,
with three exceptions, one being the hacked r11g11b10 conversions and
twiddle code which only work with block_height 2 not 1, and the last
one being blend vector type not being 128bit wide.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-05 00:29:47 +02:00
Roland Scheidegger
44993c1808 gallivm: enhance special sse2 4x4f and 2x8f -> 1x16ub conversion
There's no good reason why it can't handle 2x4f->1x8ub, 1x4f->1x4ub and
1x8f->1x8ub cases, there might be legitimate reasons why we don't have
enough input vectors for a full destination vector, and using pack
intrinsics should still be much better than using generic conversion
(it looks like convert_alpha from the blend code might hit this though
I suspect it could be avoided).

v2: add another test vector format to lp_test_conv so this gets tested.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-05 00:29:46 +02:00
Roland Scheidegger
ce82523db9 gallivm: (trivial) fix lp_build_concat_n
The code was designed to handle no-op concat but failed (unless the
caller was using same pointer for src and dst).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-05 00:29:46 +02:00
Brian Paul
f270baf074 mesa: change MAX_PROGRAM_ADDRESS_REGS to 1, clamp to it in state tracker
We've never properly supported more than one address register.  There
isn't even a field in prog_src_register or prog_dst_register to indicate
which address register to use if RelAddr!=0.

In the state tracker, clamp MaxAddressRegs against MAX_PROGRAM_ADDRESS_REGS
since many gallium drivers do support more.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65226

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-06-04 13:29:38 -06:00
Paul Berry
2fd785d126 intel: Don't try to blorp or blit CopyTexSubImage(1D_ARRAY).
Blorp and the hardware blitter can't be used to implement
CopyTexSubImage when the image type is 1D_ARRAY, because of a
coordinate system mismatch (the Y coordinate in the source image is
supposed to be matched up to the Z coordinate in the destination
texture).

The hardware blitter path (intel_copy_texsubimage) contained a perf
debug warning for this case, but it failed to actually fall back.  The
blorp path didn't even check.

Fixes piglit test "copyteximage 1D_ARRAY".

Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-04 09:14:44 -07:00
Paul Berry
32d1f423bc i965/gen6+: Fix multisample assertions in CopyTexSubImage hw blitter path.
Commit 045612c (intel: Add an assert for glCopyTexSubImage() being
called on MSAA buffers) added an assertion to intel_copy_texsubimage()
to make sure that multisampling was not in use, based on the
assumption that glCopyTexSubImage() can't legally be used with
multisampling.

However, there is one case where glCopyTexSubImage() can legally be
used with multisampling: when the source buffer is a multisampled
window system buffer.  If the source and destination color formats
don't match, the blorp path will fail, so intel_copy_texsubimage()
will be called.  In this case, we need intel_copy_texsubimage() to
return false so that we fall back to meta to do the copy.  (The
multisampled source buffer won't cause a problem for the meta path,
because it uses glReadPixels, which forces a multisample resolve).

It's still safe to assert that the destination image is
single-sampled, because it's not legal to call glCopyTexSubImage() on
multisampled textures.

Fixes some failures with piglit tests "copyteximage
{1D,2D,CUBE,RECT,2D_ARRAY}" (with "samples=..." argument).

Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-04 09:14:40 -07:00
Vinson Lee
7bafd88c15 mesa: Prevent possible out-of-bounds read by save_SamplerParameterfv.
Fixes "Out-of-bounds access" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-06-03 23:01:46 -07:00
Dave Airlie
0677ea063c i965: fix problem with constant out of bounds access (v3)
Okay I now understand why Frank would want to run away, this is
my attempt at fixing the CVE out of bounds access to constants
outside the range. This attempt converts any illegal constants
to constant 0 as per the GL spec, and is undefined behaviour.

A future patch should add some debug for users to find this out,
but this needs to be backported to stable branches.

CVE-2013-1872

v2: drop the last hunk which was a separate fix (now in master).
hopefully fix the indentations.

v3: don't fail piglit, the whole 8/16 dispatch stuff was over
my head, and I spent a while figuring it out, but this one is
definitely safe, one piglit pass extra on my Ironlake.

NOTE: This is a candidate for stable branches.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-06-04 13:50:20 +10:00