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synced 2026-05-06 05:08:08 +02:00
ilo: switch to ilo states for SOL stage
Define and use struct ilo_so_state; in ilo_context.
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parent
6b14b392d0
commit
3bc8289f49
7 changed files with 29 additions and 30 deletions
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@ -152,11 +152,10 @@ ilo_3d_pipeline_emit_draw(struct ilo_3d_pipeline *p,
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const struct pipe_draw_info *info,
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int *prim_generated, int *prim_emitted)
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{
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const bool so_enabled = (ilo->stream_output_targets.num_targets > 0);
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bool success;
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if (ilo->dirty & ILO_DIRTY_STREAM_OUTPUT_TARGETS &&
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so_enabled && !ilo->stream_output_targets.append_bitmask) {
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ilo->so.enabled && !ilo->so.append_bitmask) {
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/*
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* We keep track of the SVBI in the driver, so that we can restore it
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* when the HW context is invalidated (by another process). The value
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@ -525,7 +525,7 @@ gen6_pipeline_update_max_svbi(struct ilo_3d_pipeline *p,
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for (i = 0; i < so_info->num_outputs; i++) {
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const int output_buffer = so_info->output[i].output_buffer;
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const struct pipe_stream_output_target *so =
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ilo->stream_output_targets.targets[output_buffer];
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ilo->so.states[output_buffer];
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const int struct_size = so_info->stride[output_buffer] * 4;
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const int elem_size = so_info->output[i].num_components * 4;
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int buf_size, count;
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@ -901,9 +901,8 @@ gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline *p,
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const struct ilo_shader_state *vs = ilo->vs;
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const struct ilo_shader_state *gs = ilo->gs;
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const struct pipe_stream_output_target **so_targets =
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(const struct pipe_stream_output_target **)
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ilo->stream_output_targets.targets;
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const int num_so_targets = ilo->stream_output_targets.num_targets;
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(const struct pipe_stream_output_target **) ilo->so.states;
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const int num_so_targets = ilo->so.count;
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if (p->dev->gen != ILO_GEN(6))
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return;
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@ -394,11 +394,10 @@ gen7_pipeline_sol(struct ilo_3d_pipeline *p,
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gen6_pipeline_update_max_svbi(p, ilo, session);
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/* 3DSTATE_SO_BUFFER */
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if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh) &&
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ilo->stream_output_targets.num_targets) {
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if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh) && ilo->so.enabled) {
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int i;
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for (i = 0; i < ilo->stream_output_targets.num_targets; i++) {
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for (i = 0; i < ilo->so.count; i++) {
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const int stride = so_info->stride[i] * 4; /* in bytes */
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int base = 0;
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@ -409,7 +408,7 @@ gen7_pipeline_sol(struct ilo_3d_pipeline *p,
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}
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p->gen7_3DSTATE_SO_BUFFER(p->dev, i, base, stride,
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ilo->stream_output_targets.targets[i], p->cp);
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ilo->so.states[i], p->cp);
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}
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for (; i < 4; i++)
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@ -417,13 +416,12 @@ gen7_pipeline_sol(struct ilo_3d_pipeline *p,
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}
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/* 3DSTATE_SO_DECL_LIST */
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if (dirty_sh && ilo->stream_output_targets.num_targets)
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if (dirty_sh && ilo->so.enabled)
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p->gen7_3DSTATE_SO_DECL_LIST(p->dev, so_info, sh, p->cp);
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/* 3DSTATE_STREAMOUT */
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if (DIRTY(STREAM_OUTPUT_TARGETS) || DIRTY(RASTERIZER) || dirty_sh) {
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const unsigned buffer_mask =
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(1 << ilo->stream_output_targets.num_targets) - 1;
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const unsigned buffer_mask = (1 << ilo->so.count) - 1;
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p->gen7_3DSTATE_STREAMOUT(p->dev, buffer_mask, sh->out.count,
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ilo->rasterizer->rasterizer_discard, p->cp);
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@ -546,9 +546,7 @@ ilo_blitter_begin(struct ilo_context *ilo, enum ilo_blitter_op op)
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util_blitter_save_vertex_elements(ilo->blitter, (void *) ilo->ve);
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util_blitter_save_vertex_shader(ilo->blitter, ilo->vs);
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util_blitter_save_geometry_shader(ilo->blitter, ilo->gs);
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util_blitter_save_so_targets(ilo->blitter,
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ilo->stream_output_targets.num_targets,
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ilo->stream_output_targets.targets);
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util_blitter_save_so_targets(ilo->blitter, ilo->so.count, ilo->so.states);
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util_blitter_save_fragment_shader(ilo->blitter, ilo->fs);
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util_blitter_save_depth_stencil_alpha(ilo->blitter,
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@ -60,6 +60,8 @@ struct ilo_context {
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const struct ilo_ve_state *ve;
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struct ilo_ib_state ib;
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struct ilo_so_state so;
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struct pipe_blend_state *blend;
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struct pipe_rasterizer_state *rasterizer;
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struct pipe_depth_stencil_alpha_state *depth_stencil_alpha;
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@ -91,12 +93,6 @@ struct ilo_context {
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unsigned num_buffers;
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} constant_buffers[PIPE_SHADER_TYPES];
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struct {
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struct pipe_stream_output_target *targets[ILO_MAX_SO_BUFFERS];
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unsigned num_targets;
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unsigned append_bitmask;
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} stream_output_targets;
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struct {
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struct pipe_surface *surfaces[PIPE_MAX_SHADER_RESOURCES];
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unsigned num_surfaces;
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@ -66,4 +66,12 @@ struct ilo_ve_state {
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unsigned count;
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};
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struct ilo_so_state {
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struct pipe_stream_output_target *states[ILO_MAX_SO_BUFFERS];
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unsigned count;
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unsigned append_bitmask;
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bool enabled;
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};
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#endif /* ILO_GPE_H */
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@ -785,15 +785,16 @@ ilo_set_stream_output_targets(struct pipe_context *pipe,
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if (!targets)
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num_targets = 0;
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for (i = 0; i < num_targets; i++) {
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pipe_so_target_reference(&ilo->stream_output_targets.targets[i],
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targets[i]);
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}
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for (; i < ilo->stream_output_targets.num_targets; i++)
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pipe_so_target_reference(&ilo->stream_output_targets.targets[i], NULL);
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for (i = 0; i < num_targets; i++)
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pipe_so_target_reference(&ilo->so.states[i], targets[i]);
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ilo->stream_output_targets.num_targets = num_targets;
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ilo->stream_output_targets.append_bitmask = append_bitmask;
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for (; i < ilo->so.count; i++)
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pipe_so_target_reference(&ilo->so.states[i], NULL);
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ilo->so.count = num_targets;
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ilo->so.append_bitmask = append_bitmask;
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ilo->so.enabled = (ilo->so.count > 0);
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ilo->dirty |= ILO_DIRTY_STREAM_OUTPUT_TARGETS;
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}
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