Commit graph

198525 commits

Author SHA1 Message Date
Lionel Landwerlin
888f63cf1b anv/iris: leave 4k alignments for clear colors with modifiers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 17f97a69c1 ("iris: Reduce clear color state alignment to 64B")
Fixes: 063715ed45 ("anv: Reduce clear color state alignment to 64B")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12195
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13057
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32422>
2024-12-02 12:51:45 +00:00
Collabora's Gfx CI Team
52f13f5603 Uprev Piglit to 468221c722481c470e6a23760b914c33143c2af6
d04d6fff00...468221c722

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32272>
2024-12-02 12:13:05 +00:00
Sergi Blanch Torne
a4e3ff0464 Revert "ci: disable Collabora's farm due to maintenance"
This reverts commit fd14b34923.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32420>
2024-12-02 11:38:20 +00:00
Michel Dänzer
8197111881 winsys/amdgpu: Always use amdgpu_device_get_fd for aws->fd
If the caller passed in the same DRM file description, use it for sws->fd
as well. This is simpler than the previously reverted commit and also
fixes https://gitlab.freedesktop.org/mesa/mesa/-/issues/12208.

v2:
* Move fallback sws->fd assignment to proper scope, fixes CI failures.
* Remove close(sws->fd) from amdgpu_winsys_create failure path, it can
  never be a valid file descriptor != aws->fd there.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32377>
2024-12-02 10:38:22 +00:00
Michel Dänzer
f873ee506f Revert "winsys/amdgpu: fix FD mismatch"
This reverts commit 9223528059.

Not needed. (The amdgpu_screen_winsys::input_fd reference in the comment
didn't make sense, there was no such thing)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32377>
2024-12-02 10:38:22 +00:00
Rhys Perry
fd19ff0b9e aco: force linear for event_vmem_sample and event_vmem_bvh
I don't know if this issue affects GFX12, but workaround it anyway to be
safe.

fossil-db (gfx1200):
Totals from 3463 (4.36% of 79395) affected shaders:
Instrs: 9794280 -> 9833253 (+0.40%); split: -0.00%, +0.40%
CodeSize: 52306040 -> 52457988 (+0.29%); split: -0.01%, +0.30%
Latency: 90549385 -> 93617517 (+3.39%); split: -0.00%, +3.39%
InvThroughput: 13189030 -> 13602942 (+3.14%); split: -0.00%, +3.14%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32373>
2024-12-02 10:13:39 +00:00
Rhys Perry
86c63b29bc aco/gfx12: insert wait between VMEM WaW
https://github.com/llvm/llvm-project/pull/105549

fossil-db (gfx1200):
Totals from 1783 (2.25% of 79395) affected shaders:
Instrs: 7398391 -> 7404566 (+0.08%); split: -0.00%, +0.08%
CodeSize: 38862456 -> 38886364 (+0.06%); split: -0.00%, +0.06%
Latency: 83191513 -> 84211504 (+1.23%); split: -0.00%, +1.23%
InvThroughput: 15185936 -> 15345744 (+1.05%); split: -0.01%, +1.06%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32373>
2024-12-02 10:13:39 +00:00
Rhys Perry
9f3607de76 nir/tests: fix SSA dominance in opt_if_merge tests
It isn't necessary for these ALU instructions to be used in the next IF.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: c437f2e79c ("nir/tests: Add tests for opt_if_merge")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12211
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32391>
2024-12-02 09:38:22 +00:00
Benjamin Cheng
e9d9c67eab radv/video: enable by default on vcn2/3 with latest fw
The latest FW in the linux-firmware repo provides the required features
to pass all the CTS tests.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32407>
2024-12-02 08:30:08 +00:00
Sergi Blanch Torne
fd14b34923 ci: disable Collabora's farm due to maintenance
Planned downtime in the farm:
* Start: 2024-12-02 08:00 UTC
* End: 2024-12-02 14:00 UTC

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32183>
2024-12-02 07:07:07 +00:00
David Rosca
76e3004fef radv/video: Always use setup reference slot when valid
Reviewed-by: Benjamin Cheng <ben@bcheng.me>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10977
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32414>
2024-12-02 06:26:34 +00:00
David Rosca
ef6facac15 radv/video: Fix IB signature checksum
Reviewed-by: Benjamin Cheng <ben@bcheng.me>
Fixes: 152b06acd8 ("ac/vcn: allow sq signature package to be skipped")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32414>
2024-12-02 06:26:34 +00:00
Timothy Arceri
6ca81adffc nir: allow loops with unknown induction var initialiser to unroll
If the condition of the loop terminator is based on an unsigned value we
can in some cases find the max number of possible loop trips. With the
max loop trips know a complex unroll can unroll the loop.

For example:

   uniform uint x;
   uint i = x;
   while (true) {
      if (i >= 4)
         break;

      i += 6;
   }

The above loop can be unrolled even though we don't know the initial
value of the induction variable because it can have at most 1 iteration.

There were no changes with my shader-db collection. Change was inspired
by MR #31312 where builtin shader code failed to unroll.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31701>
2024-12-02 11:44:33 +11:00
Dave Airlie
fcaf0f2590 vulkan: update to 302 headers for av1 encode
Some of the spirv AMDX stuff probably broke things, but it should
still build.

Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32401>
2024-12-02 06:29:00 +10:00
Connor Abbott
8fe3674df8 vulkan/runtime,radv: Add shared BVH building framework
This is mostly adapted from radv's BVH building. This defines a common
"IR" for BVH trees, two algorithms for constructing it, and a callback
that the driver implements for encoding. The framework takes care of
parallelizing the different passes, so the driver just has to split the
encoding process into "stages" and implement just one part for each
stage.

The runtime changes are:
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
The radv changes are;

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31433>
2024-12-01 20:08:35 +01:00
Connor Abbott
f8b584d6a5 vulkan/runtime,radv: Add shared BVH building framework
This is mostly adapted from radv's BVH building. This defines a common
"IR" for BVH trees, two algorithms for constructing it, and a callback
that the driver implements for encoding. The framework takes care of
parallelizing the different passes, so the driver just has to split the
encoding process into "stages" and implement just one part for each
stage.

The runtime changes are:
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
The radv changes are;

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31433>
2024-12-01 16:08:06 +00:00
Konstantin
d19af11e49 vulkan/meta: Add a pipeline cache
RADV has a pipeline cache for meta shaders that can be used. It is also
required to correctly identify the pipelines as meta pipelines.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31433>
2024-12-01 16:08:06 +00:00
Connor Abbott
c1c39116a7 vulkan/runtime: Add driver callbacks for BVH building
All of these are functions that could reasonably be incorporated into a
Vulkan extension, but are currently missing. While we could in theory do
BVH building without them, using them simplifies the code significantly
and both radv and turnip can reasonably implement them.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31433>
2024-12-01 16:08:06 +00:00
Job Noorman
8ae5b27ee0 ir3: reformat after refactoring in previous commit
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32088>
2024-12-01 10:21:26 +00:00
Job Noorman
fda91b49d7 ir3: refactor builders to use ir3_builder API
All functions that used to take an ir3_block as argument to append
instructions to now take an ir3_builder as argument.

Add an ir3_builder field to ir3_context and replace all uses of
ir3_context::block for creating instructions with ir3_context::build.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32088>
2024-12-01 10:21:26 +00:00
Job Noorman
6c38402e9a ir3: use generic INSTR0 implementation for ir3_NOP
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32088>
2024-12-01 10:21:26 +00:00
Job Noorman
af92e4934e ir3: add ir3_after_instr_and_phis helper
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32088>
2024-12-01 10:21:26 +00:00
Job Noorman
62b23f175e ir3: don't update builder cursor for IR3_CURSOR_AFTER_BLOCK
During instruction selection, instructions are sometimes emitted to
blocks other than the current one. For example, to predecessor blocks
for phi sources or to the first block for inputs. For those cases, a new
builder is created to emit at the end of the target block. However, if
the target block happens to be the same as the current block, the main
builder would not be updated to point past the new instructions.
Therefore, don't update the cursor when it points to the end of a block
to ensure that new instructions will always be added at the end.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32088>
2024-12-01 10:21:26 +00:00
Arseny Kapoulkine
6a3944a195 radv: On GFX11, use box sorting heuristic based on ray flags
Use box with largest ray interval for shadow rays (terminate on first
hit) as it maximizes the probability of finding some object in that box;
for reflection (closest hit) rays, use midpoint instead, which defers
processing of larger boxes the ray origin is in in favor of smaller
boxes closer to origin.

Since the sorting mode must be uniform, when terminate_on_first_hit flag
is divergent, we leave it as closest.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32416>
2024-12-01 05:20:58 +00:00
Robert Mader
379de4cdce freedreno: Support offset query for multi-planar planes
This allows `gbm_bo_get_offset()` to return the correct offset for e.g.
the second plane of a resource with the NV12 format. Crucially this
fixes direct scanout / hardware plane usage in Mutter and possibly other
clients.

While on it also add support for stride, modifier and n_planes queries.
The later two should not change in behavior and just safe a few CPU
cycles. The stride query support in theory fixes queries for multi-plane
formats, however in practice most/all currently used formats such as NV12,
P010 and YUV420 use the same stride for all planes.

Cc: mesa-stable
Acked-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Robert Mader <robert.mader@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32282>
2024-11-29 18:10:28 +01:00
Job Noorman
1cd09a0177 tu: advertise VK_SUBGROUP_FEATURE_ROTATE_CLUSTERED_BIT_KHR
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:48 +00:00
Job Noorman
659e033897 ir3: lower clustered rotates to shuffles
shfl.rdown only works for the non-clustered case.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:48 +00:00
Job Noorman
d5d0628728 nir/lower_subgroups: add option to only lower clustered rotates
On ir3, we have native support for full rotates but not for clustered
ones.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:48 +00:00
Job Noorman
eba6a70a66 tu: advertise VK_SUBGROUP_FEATURE_CLUSTERED_BIT
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:48 +00:00
Job Noorman
c44f998d69 ir3: add support for clustered subgroup reductions
This is implemented differently depending on the cluster size:
- At most 8: in this case, executing brcst.active will leave the
  reduction in the last invocation of each cluster. Simply iterate the
  clusters and broadcast the last invocation to the rest.
- Otherwise, also iterate the clusters but execute the usual
  reduce_clusters_ir3 loop for each of them.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:48 +00:00
Job Noorman
5dbd2b08f4 nir/lower_subgroups: disable boolean reduce when not supported
lower_boolean_reduce only supports ballot_components == 1. Fall back to
lower_scan_reduce when this is not the case.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:48 +00:00
Job Noorman
493f7b8084 nir/lower_subgroups: add extra filter data to options
It might be convenient for filter implementations to have access to
extra information. This will be used, for example, by ir3 to access
compiler features.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:48 +00:00
Job Noorman
c789a0a3d3 ir3: rename cluster_size to brcst_cluster_size
In preparation for the next commit where we'll want to use cluster_size
for the intrinsic's cluster size.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:48 +00:00
Job Noorman
0be9ff47b4 ir3: add helper to get the subgroup size
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:47 +00:00
Job Noorman
2e2a36ddb0 ir3: add codegen for read_getlast_ir3
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:47 +00:00
Job Noorman
e6c63a88fb nir: add read_getlast_ir3 intrinsic
Like read_first_invocation but using getlast. Note that I intentionally
used the name of the ir3 instruction in the name as its semantics are
tricky to exactly describe otherwise.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:47 +00:00
Job Noorman
7bab441ae6 ir3: remove unused ir3_nir_lower_64b_subgroups
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:47 +00:00
Job Noorman
5e9cf354ca ir3: use generic lowering for 64b scan/reduce
Now that we use shfl for lowering shuffle operations, the generic
lowering of scan/reduce to shuffles results in faster code than our
custom loop for 64b operations.

Note that this was measured using a micro benchmark on full subgroups.
The generic lowering might be slower when not all invocations are active
but this should be a rare case.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:47 +00:00
Job Noorman
60e1615ced nir/lower_subgroups: support unknown subgroup size
Some targets (e.g., ir3) don't always know the exact subgroup size.
Calculate the maximum subgroup size in that case by multiplying
ballot_components and ballot_bit_size.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31731>
2024-11-29 16:22:47 +00:00
Simon Perretta
cee548095a CODEOWNERS: update for new pco compiler tree
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
e67e44522f pco: initial validation boilerplate and SSA checks
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
b35ba3a8a5 pco: modifier propagation optimization, shared opt context boilerplate
Tackles cases where mod propagation candidate ops have a restriction on one
of their sources but are commutative, thus allowing the restriction to be
worked around by swapping the sources.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
527b38d1fd pvr, pco: rewrite compiler/driver interface for vs & fs I/O
Basic vertex/fragment shader I/O and sysval allocation rewritten to use
the new compiler/driver interface, with allocation moved entirely into
the driver.

RHW coeffs now only emitted when required.

Boilerplate support for converting formats for vs inputs/fs outputs.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
99852fbe4d pco: track the number of bytes encoded for each function
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
0f720a5c98 pco: add opt subpass for propagating comps referencing hw regs
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
37d4791343 pco: vec coalescing improvement to register allocation
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
ce8392024d pco: add helpers for overriding ref chans and offsetting vals
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
71480c075e pco: temporarily add hardcoded vs/fs I/O for testing, BXS-4-64 iteration support
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
cf83858a47 pco: add mappings and translation for ditr
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00
Simon Perretta
a89a9b65f8 pco: re-indexing debug option and additional vector and component tracking
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
2024-11-29 15:14:12 +00:00