Commit graph

134480 commits

Author SHA1 Message Date
Erik Faye-Lund
84fd3b7709 zik: correct spir-v caps for textures and images
There's a couple of minor issues with these the way they where:

1. All shader stages can perform texturing. So let's check for textures
   instead of fragment-shader
2. Not all implementations support StorageImageExtendedFormats. We don't
   expose image support for those implementations, but we shouldn't
   enable the cap just because we're texturing.

Both of these issues can be tackled by splitting these into texturing
and images conditionals.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
2021-02-02 16:00:37 +00:00
Erik Faye-Lund
7ce9c029b1 zink: only emit cap when needed
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
2021-02-02 16:00:37 +00:00
Erik Faye-Lund
b6da248c0e zink: only emit SpvCapabilityDerivativeControl when needed
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
2021-02-02 16:00:37 +00:00
Erik Faye-Lund
36a4b423fe zink: correct return-type for function
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
2021-02-02 16:00:37 +00:00
Erik Faye-Lund
9fbacf5bcf zink: be more careful about limits when unsupported
These limits are dependent on feature caps, so let's try to thread
a bit more carefully when the cap is unsupported.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
2021-02-02 16:00:37 +00:00
Erik Faye-Lund
5b9042577c zink: remove stale TODO
By now, I think we're fairly sure about this one ;)

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
2021-02-02 16:00:37 +00:00
Jason Ekstrand
f064b7a42c nir: Add some ssa-only fast-paths for nir_src rewrite
Basically every pass in NIR uses nir_ssa_def_rewrite_uses which calls
nir_instr_rewrite_src which is fairly complex because it handles all
sorts of non-SSA cases.  Since we already know a priori that every
source written by nir_ssa_def_rewrite_uses is SSA, we can check new_src
once at the top of the function and cut out all that complexity.

While we're at it, we expose a new SSA-only nir_ssa_def_rewrite_uses_ssa
helper which takes an SSA def which avoids the one SSA check.  It's also
more convenient 90% of the time.

Compile time as tested by Rhys Perry <pendingchaos02@gmail.com>

    Difference at 95.0% confidence
        -797.166 +/- 418.649
        -0.566174% +/- 0.296441%
        (Student's t, pooled s = 325.459)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8790>
2021-02-02 15:35:55 +00:00
SureshGuttula
592c17b39d va/picture : Added failure check for stability
This patch created to exit from for loop incase handle function
returns error vaStatus. This will help to capture the correct
failure return to application.

Signed-off-by: SureshGuttula <sguttula@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8679>
2021-02-02 13:38:22 +00:00
Lionel Landwerlin
eec2d4e466 anv: switch intel perf queries to query layout
Apart from the single additional marker field, these queries will now
use the same layout as all other drivers.

This should allow us to modify a single component to add an additional
register for new metrics.

v2: Capture the query beging registers in reverse order to ensure
    timestamp is as close as possible from measured draw call.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
8ca1f488e6 anv: switch khr perf query code to use query layout
This unifies performance data gathering between the GL & Vulkan
drivers.

v2: Also move all NOOPs to before the query, leaving none inside

v3: Capture the query beging registers in reverse order to ensure
    timestamp is as close as possible from measured draw call.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
76bba61e0b anv: compute commands required to implement perf queries
We'll use this later to try to limit the number of NOOPs emitted for
self modifying batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
185df6ac9c intel/perf: drop the special READ_REG operator
Makes things a bit more uniform.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
f721f2ad05 intel/perf: add DG1 support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
1b335bc55a intel/perf: add RKL support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
4d6741b11b intel/dev: identify rocketlake
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
1b3443fbd9 intel/perf: break TGL perf configs in GT1/2
Programming and equations are different enough that we really need 2
files.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
f97fc0ff8b intel/dev: identify tigerlake
We'll need that to pick the right query sets between TGL/RKL/DG1.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
6afe5d3624 intel/perf: add async compute metrics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
7335faa1a9 intel/perf: small ICL equation refactor
No functional changes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
b5f32e948f intel/perf: update files from IGT
IGT has received a bunch of updates, this is resyncing the files with
it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
5d0886089e intel/perf: remove reordering script
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
01179d2bc3 intel/perf: reorder xml files
Make the file match the order of the ones from IGT (which have changed
because of python2->3 transition).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:55 +00:00
Lionel Landwerlin
12ee1ec25e intel/perf: add reorder script
When transitioning the oa-*.xml files from Gputop to IGT, we also had
to deal with a python2->3 transition. Unfortunately the implementation
dependent hash table ordering leaked into the XML files and so things
changed quite a bit.

This script reorders things from the old to the new order in the
existing files.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Lionel Landwerlin
404d0f7626 intel/perf: rename lkf into ehl
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Lionel Landwerlin
3ed29f944c anv: remove unused query pool field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Lionel Landwerlin
0e64912446 anv: fix layout comment
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Lionel Landwerlin
3c51325025 intel/perf: switch query code to use query layout
That way we can describe new registers to that could be used both by
Anv & Iris/i965 without having to modifying code in multiple places.

v2: Do reverse order for begin queries so that we have MI_RPC as close
    as possible from the drawcall

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Lionel Landwerlin
8750f43a90 intel/perf: add performance query layout using MI_SRM
For all generations supported we had a layout describing what register
to store to implement a MI_RPC replacement.

This is because, on Gen12 we need to snapshot OAG registers to get
correct values for the perf equations. There, the MI_RPC instruction
captures OAR register which do not have all the information we need.

v2: Fix commented code for debug (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Lionel Landwerlin
f32d1bf529 intel/perf: query register descriptions
This will be useful when we implement queries using a series of MI_SRM
instead of MI_RPC.

Unfortunately on Gen12, the MI_RPC command sources values from the OAR
unit which has a similar series of register as the OAG unit but some
of the configuration of HW doesn't reach OAR so we have to snapshot
OAG manually instead.

v2: Fix comments
    Use const

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Lionel Landwerlin
a6e980e9bf intel/perf: prep work to enable new perf counters
Those are not part of the OA reports and need some additional
scaffolding. Those counters are only available when doing queries as
we need to emit MI_SRMs to record them.

Equations making use of those counters are not there yet, they will
come in a follow up commit updating a bunch of oa-*.xml files.

v2: Fix typo

v3: Use PERF_CNT_VALUE_MASK (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Lionel Landwerlin
969f6efbc2 genxml: PERFCNT registers are available since HSW
We were using those registers on Gen7.5 in the GL driver already, we
just need them in Genxml for Anv too.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
2021-02-02 13:25:54 +00:00
Andrii Simiklit
adc7f97a70 iris: don't emit IRIS_DIRTY_VF depending on trash in restart_index
The `restart_index` field can be uninitialized if `primitive_restart`
is false so we have to track `restart_index` changes
only if `primitive_restart` is true

Here is a valgrind warning:
Conditional jump or move depends on uninitialised value(s)
==52021==    at 0x6D44968: iris_update_draw_info (iris_draw.c:102)
==52021==    by 0x6D450B5: iris_draw_vbo (iris_draw.c:273)
==52021==    by 0x642FD8E: cso_multi_draw (cso_context.c:1708)
==52021==    by 0x5C434D3: st_draw_gallium (st_draw.c:271)
==52021==    by 0x5DF5F1B: _mesa_draw_arrays (draw.c:554)
==52021==    by 0x5DF68F7: _mesa_DrawArrays (draw.c:768)
==52021==    by 0x49011F2: stub_glDrawArrays (piglit-dispatch-gen.c:12181)
==52021==    by 0x11C611: piglit_display (shader_runner.c:4549)
==52021==    by 0x4994D83: process_next_event (piglit_x11_framework.c:137)
==52021==    by 0x4994E47: enter_event_loop (piglit_x11_framework.c:153)
==52021==    by 0x49939A4: run_test (piglit_winsys_framework.c:88)
==52021==    by 0x49821A9: piglit_gl_test_run (piglit-framework-gl.c:229)

v2: - don't propagate trash to state->cut_index
    (Kenneth Graunke <kenneth@whitecape.org>)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8409>
2021-02-02 13:16:07 +00:00
Boris Brezillon
470d3a3640 panfrost: Update ctx->batch when a fresh batch is requested
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:49:58 +01:00
Boris Brezillon
834bb5e54c panfrost: Add a panfrost_compile_shader() helper
This deduplicates the

   if (pan_is_bifrost())
      return bifrost_compile_shader_nir();
   else
      return midgard_compile_shader_nir();

pattern.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:04:15 +01:00
Boris Brezillon
89cfa4180b panfrost: Use dev->arch where appropriate
The architecture has already been extracted in panfrost_open_device()
don't do it again.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:04:15 +01:00
Boris Brezillon
d78f686ad1 panfrost: Rename and move pan_render_condition_check()
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:04:15 +01:00
Boris Brezillon
3913089d2d panfrost: Set attribs and attrib_bufs to NULL when attrib_count = 0
It's just easier to read pandecode traces when those pointers are set
to NULL for the attribute_count=0 case.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:04:15 +01:00
Boris Brezillon
81a21ea9cd panfrost: Only allocate the extra attribute buffer entry on Bifrost
Bifrost needs an empty attribute buffer entry to tell the prefecter it
should stop fetching attribute buffers, but Midgard doesn't have this
constraint. It's also useless to have 2 empty entries for the instance or
image case.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:04:15 +01:00
Boris Brezillon
63d9e412ec panfrost: Don't memset the last attribute buffer entry twice
It's already done a few lines below.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:04:15 +01:00
Boris Brezillon
4544d00e71 panfrost: Get rid of IS_BIFROST
Extract this information from dev->arch, and provide a helper to hide
this check.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:04:15 +01:00
Boris Brezillon
ec6c6f610c panfrost: Fix tiler job injection (again)
2f1947b39c ("panfrost: Fix tiler job injection") had the tests
inverted: WRITE_VALUE jobs are only needed on Midgard, not Bifrost.

Cc: mesa-stable
Fixes: 2f1947b39c ("panfrost: Fix tiler job injection")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
2021-02-02 09:04:15 +01:00
Arcady Goldmints-Orlov
93f8f83a95 broadcom/compiler: improve generation of if conditions
Where it is safe to do so, avoid the generation of code to convert a
condition code into a boolean which is then tested to generate a
condition code. This is only done in uniform ifs, and only for condition
values that are SSA and only used once (in that if statement).

shader-db relative to MR 7726:

total instructions in shared programs: 8985667 -> 8974151 (-0.13%)
instructions in affected programs: 390140 -> 378624 (-2.95%)
helped: 810
HURT: 276
helped stats (abs) min: 1 max: 49 x̄: 17.77 x̃: 16
helped stats (rel) min: 0.10% max: 33.63% x̄: 7.97% x̃: 6.45%
HURT stats (abs)   min: 1 max: 46 x̄: 10.42 x̃: 10
HURT stats (rel)   min: 0.16% max: 21.54% x̄: 2.26% x̃: 2.03%
95% mean confidence interval for instructions value: -11.46 -9.75
95% mean confidence interval for instructions %-change: -5.76% -4.97%
Instructions are helped.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8709>
2021-02-02 06:55:49 +00:00
Marek Olšák
b60dfa2c09 radeon: decrease the size of radeon_cmdbuf by switching prev fields to uint16
This also removes the 32-bit hole in radeon_cmdbuf.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8434>
2021-02-02 05:42:32 +00:00
Marek Olšák
34114e1dcb radeonsi: tune NGG shader culling vertex threshold for each chip
These are based on my testing and estimation.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8434>
2021-02-02 05:42:32 +00:00
Marek Olšák
ffbf3a5f8b radeonsi: simplify the NGG culling condition in si_draw_vbo
Changes:

- disallow NGG culling for GS, fast launch for tess using template args
  (GS can't do NGG culling, tess can't do fast launch)

- skip checking current_rast_prim with tessellation
  (bake the condition into ngg_cull_vert_threshold)

- use only 1 vertex count threshold for enabling NGG shader culling
  to simplify it. I think it doesn't have a big impact. The threshold
  computation depends on more parameters than just fast launch.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8434>
2021-02-02 05:42:32 +00:00
Marek Olšák
7581743510 radeonsi: set current_rast_prim at bind time for tess and GS
It doesn't have to be done in draw_vbo.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8434>
2021-02-02 05:42:32 +00:00
Mark Janes
2edfb27913 intel: combine common gather routines in INTEL_MEASURE
Anv and iris had separate, similar routines to gather intel_measure
timestamps.  Timestamps are now managed within intel_measure, allowing
those routines to be consolidated.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Mark Janes
d6fc72e286 intel: support secondary command buffers in INTEL_MEASURE
When a secondary command buffer is encountered, insert an event that
links to the new batch.

This commit leaves intel_measure timestamp buffer objects mmapped,
which is more efficient than mapping/unmapping several times.  With
the BOs mapped at all times, timestamp buffers can be managed directly
by intel_measure, where it will iterate over timestamps of linked
secondary buffers.

With timestamp buffers managed by intel_measure, a more efficient and
accurate check for render completion can be moved into intel_measure
from anv/iris.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Mark Janes
9eacbfaf7b intel: stop tracking submission state in INTEL_MEASURE
With secondary command buffers, it is inconvenient to track whether a
batch has been submitted and needs to be gathered.  Instead, always
check for completed snapshots before destroying a command buffer.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00
Kenneth Graunke
f7d4ebbf86 iris: add hooks to call INTEL_MEASURE
These hooks were written in the initial IRIS_MEASURE implementation.
Minor changes by Mark Janes <markjanes@swizzler.org> to adapt to the
INTEL_MEASURE reimplementation.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
2021-02-01 17:24:57 -08:00