Commit graph

64432 commits

Author SHA1 Message Date
Kenneth Graunke
82ddd517af i965/eu: Refactor jump distance scaling to use a helper function.
Different generations of hardware measure jump distances in different
units.  Previously, every function that needed to set a jump target open
coded this scaling, or made a hardcoded assumption (i.e. just used 2).

Most functions start with the number of instructions to jump, and scale
up to the hardware-specific value.  So, I made the function match that.

Others start with a byte offset, and divide by a constant (8) to obtain
the jump distance.  This is actually 16 / 2 (the jump scale for Gen5-7).

v2: Make the helper a static inline defined in brw_eu.h, instead of
    an actual function in brw_eu_emit.c (as suggested by Matt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
a1c899c718 i965/eu: Set UIP on ELSE instructions on Broadwell.
Broadwell adds UIP on ELSE instructions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
7d41170b62 i965/eu: Make it clear that brw_patch_break_count only runs on Gen4-5.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
0457464c33 i965/eu: Make it clear that brw_find_loop_end only runs on Gen6+.
It has Gen6+ knowledge baked in, and indeed is only called for Gen6+,
but it wasn't immediately obvious that this was the case.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
0d6adce469 i965/eu: Port Broadwell CMP destination type hack to brw_eu_emit.c.
See gen8_generator::CMP().

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
49519a1b63 i965/eu: Explicitly disable instruction compaction on Broadwell for now.
Until now, it's been off implicitly: we never call the compactor
function.  When we merge the generators, we'll start calling it, so we
should make it do nothing.

Matt will enable instruction compaction properly later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:33 -07:00
Kenneth Graunke
8609df97a0 i965/eu: Use Haswell atomic messages on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:03:45 -07:00
Kenneth Graunke
e1bd2ca28a i965/eu: Change gen == 7 to gen >= 7 in a couple brw_eu_emit.c cases.
Broadwell is going to use the brw_eu_emit.c code soon.  We want to get
the fake MRF handling and URB HWord channel mask handling.

We don't need the CMP thread switch workaround, though.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:01:52 -07:00
Ben Widawsky
38e181bad2 i965/clip: Removing scissor atom
Now that we no longer use ctx->DrawBuffer->_Xmin and related fields to
program the screen-space viewport extents, we don't depend on any
scissoring state.  So we can drop the +_NEW_SCISSOR dependency.

On GEN8, a change in scissor state does not effect anything for the
clipper/sf hardware state. The hardware will always do the right thing
once the viewport extents are programmed. We can therefore remove the
unecessary state emission.

Ken originally spotted this.

v2: Reword the commit message. Remove spurious hunk.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 17:13:36 -07:00
Ben Widawsky
f6725d627c i965/guardband: Enable for all viewport dimensions (GEN8+)
The goal of guardband clipping is to try to avoid 3d clipping because it
is an expensive operation. When guardband clipping is disabled, all
geometry that intersects the viewport is sent to the FF 3d clipper.
Objects which are entirely enclosed within the viewport are said to be
"trivially accepted" while those entirely outside of the viewport are,
"trivially rejected".

When guardband clipping is turned on the above behavior is changed such
that if the geometry is within the guardband, and intersects the
viewport, it skips the 3d clipper. Prior to GEN8, this was problematic
if the viewport was smaller than the screen as it could allow for
rendering to occur outside of the viewport. That could be mitigated if
the programmer specified a scissor region which was less than or equal
to the viewport - but this is not required for correctness in OpenGL. In
theory you could be clever with the guardband so as not to invoke this
problem. We do not do this, and have no data that suggests we should
bother (nor the converse data).

With viewport extents in place on GEN8, it should be safe to turn on
guardband clipping for all cases

While here, add a comment to the code which confused me thoroughly.

v2: Update grammar in commit message. Reword comments based on Ken's
suggestion.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 17:13:36 -07:00
Ben Widawsky
1a20e38ccf i965: Simplify viewport extents programming on GEN8
Viewport extents are a 3rd rectangle that defines which pixels get
discarded as part of the rasterization process. The actual pixels drawn
to the screen are an intersection of the drawing rectangle, the viewport
extents, and the scissor rectangle. It permits the use of guardband
clipping in all cases (see later patch). The actual pixels drawn to the
screen are an intersection of the drawing rectangle, the viewport
extents, and the scissor rectangle.

Scissor rectangle is not super important for this discussion as it should
always help do the right thing provided the programmer uses it.

switch (viewport dimensions, drawrect dimension) {
   case viewport > drawing rectangle: no effects; break;
   case viewport == drawing rectangle: no effects; break;
   case viewport < drawing rectangle:
      Pixels (after the viewport transformation but before expensive
      rastersizing and shading operations) which are outside of the
      viewport are discarded.
}

I am unable to find a test case where this improves performance, but in
all my testing it doesn't hurt performance, and intuitively, it should
not ever hurt performance. It also permits us to use the guardband more
freely (see upcoming patch).

v2: Updating commit message.

v3: Commit message updates requested by Ken

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 17:13:36 -07:00
Ben Widawsky
109d420f42 i965/guardband: Improve comments for guardband clipping
While working in this part of the code I had a great deal of trouble
understanding what it was trying to do, and matching it with the spec.
(mostly due bad wording in the PRM). To help future people, I've cleaned
up the wording and provided some ascii art.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-10 17:13:36 -07:00
Kenneth Graunke
31f1cbc24d i965: Support the allow_glsl_extension_directive_midshader option.
This adds support for Marek's new driconf parameter, which avoids
totally white rendering in Unigine Valley (which attempts to enable
the GL_ARB_sample_shading extension in an illegal place).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75664
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-10 16:22:31 -07:00
Connor Abbott
b6df68ba56 i965/fs: set virtual_grf_count in assign_regs()
This lets us call dump_instructions() after register allocation without
failing an assertion.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.abbott@intel.com>
2014-08-10 15:00:53 -07:00
Connor Abbott
58007aec41 i965/fs: don't read from uninitialized memory while assigning registers
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.abbott@intel.com>
2014-08-10 15:00:52 -07:00
Matt Turner
59a26a0554 i965/fs: Fix bad whitespace. 2014-08-10 15:00:52 -07:00
Niels Ole Salscheider
3d5e247de6 gallium/radeon: Set gpu_address to 0 if r600_virtual_address is false
Without this patch I get the following during DMA transfers:
[drm:radeon_cs_ib_chunk] *ERROR* Invalid command stream !
radeon 0000:01:00.0: CP DMA dst buffer too small (21475829792 4096)

This is a fixup for e878e154cd.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-10 12:54:34 +02:00
Marek Olšák
a65611f70a radeonsi: simplify constant buffer upload for big endian
Point util_memcpy_cpu_to_le32 to a buffer storage directly.

v2: simplify more

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-10 12:52:13 +02:00
Marek Olšák
b1843a2d2a winsys/radeon: fix compile warnings 2014-08-09 23:48:41 +02:00
Marek Olšák
b5f877ef7e r600g/compute: fix compile warnings
Trivial.
2014-08-09 23:41:16 +02:00
Marek Olšák
3d06952d9e r300g: handle new shader caps
Trivial.
2014-08-09 23:41:16 +02:00
Marek Olšák
955505f6ff radeonsi: fix CMASK and HTILE allocation on Tahiti
Tahiti has 12 tile pipes, but P8 pipe config.

It looks like there is no way to get the pipe config except for reading
GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes,
so we can't use that for Hawaii.

This fixes a regression caused by 9b046474c9
on Tahiti.

v2: add an assertion and print an error on failure

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-09 23:41:16 +02:00
Marek Olšák
00ddf7a016 gallium/radeon: remove r600_resource_va
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:16 +02:00
Marek Olšák
8c235465cd gallium/radeon: use gpu_address from r600_resource
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:16 +02:00
Marek Olšák
f6c392a270 r600g: use gpu_address from r600_resource
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
1c03a690bf radeonsi: use gpu_address from r600_resource
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
e878e154cd gallium/radeon: store VM address in r600_resource
This will help to get rid of the buffer_get_virtual_address calls.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
43b5c34cc3 r600g: remove useless r600_resource_va calls
R600-R700 don't support virtual memory.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
0e229b8c5a radeonsi: always prefer SWITCH_ON_EOP(0) on CIK
The code is rewritten to take known constraints into account, while always
using 0 by default.

This should improve performance for multi-SE parts in theory.

A debug option is also added for easier debugging. (If there are hangs,
use the option. If the hangs go away, you have found the problem.)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver
2014-08-09 23:41:15 +02:00
Marek Olšák
515269b3a7 radeonsi: fix a hang with instancing in Unigine Heaven/Valley on Hawaii
This isn't documented anywhere, but it's the only thing that works
for this case.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
085a861545 radeon,r200: fix buffer validation after CS flush
This validates all bound buffers (CB, ZB, textures, DMA) at the beginning
of CS. This fixes "bo->space_accouned" assertion failures.

Tested by: Jochen Rollwagen <joro-2013@t-online.de>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
0b5d88a518 st/mesa: fix blit-based partial TexSubImage for 1D arrays
This fixes piglit spec/EXT_texture_array/render-1darray.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
56286834b8 st/mesa: fix DrawPixels(GL_STENCIL_INDEX)
This is a bug which was probably uncovered recently by Jason's commits
and broke this.

The problem is _mesa_base_tex_format(GL_STENCIL_INDEX) returns -1.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
88e0a2f88b st/mesa: dump TGSI before calling into the driver
If the driver crashes in create_xx_shader, you want to see the shader.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-08-09 23:41:15 +02:00
Jon TURNEY
a2e1dc0cce configure.ac: Use LIBS rather than LDFLAGS to add -ldl to dladdr check
ec8ebff "Check for dladdr()" erroneously uses LDFLAGS rather than LIBS to add
-ldl to the dladdr check.

Replace the workaround in 39a4cc4 of explicitly checking in libdl, with a more
correct approach of using LIBS.

Signed-off-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Pali Rohár <pali.rohar@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-08-09 11:18:31 +01:00
Eric Anholt
7b4b60b7e5 vc4: Add support for the COS instruction. 2014-08-08 18:59:47 -07:00
Eric Anholt
663ffff0e7 vc4: Add support for the SIN instruction.
v2: Rebase on helpers.
2014-08-08 18:59:47 -07:00
Eric Anholt
d815b2490b vc4: Fix register aliasing for packing of scaled coordinates.
Fixes glean fragProg1's "ADD test" and likely many others.
2014-08-08 18:59:47 -07:00
Eric Anholt
9492eb588d vc4: Add some debug code for forcing fragment shader output color. 2014-08-08 18:59:47 -07:00
Eric Anholt
961715eab2 u_primconvert: Copy min/max_index from the original primitive.
These values are supposed to be the minimum/maximum index values used to
read from the vertex buffers.  This code either copies index values out of
the old IB (so, same min/max as the original draw call), or generates a
new IB (using index values between the start and the start + count of the
old array draw info, which just happens to be what min/max_index are set
to by st_draw.c).

We were incorrectly setting the max_index in the
converting-from-glDrawArrays case to the start vertex plus the number of
vertices generated in the new IB, which broke QUADS primitive conversion
on VC4 (where max_index really has to be correct, or the kernel might
reject your draw call due to buffer overflow).

Reviewed-by: Rob Clark <robclark@freedesktop.org> (from verbal description
             of the patch)
2014-08-08 18:59:47 -07:00
Eric Anholt
1d03692f78 vc4: Fix using and emitting the 1/W from the vertex/coord shaders.
v2: Rebase on helpers change.
2014-08-08 18:59:47 -07:00
Eric Anholt
88bc5baa00 vc4: Add support for swizzles of 32 bit float vertex attributes.
Some tests start working (useprogram-flushverts, for example) due to
getitng the right vertices now.  Some that used to pass start failing with
memory overflow during binning, which is weird (glsl-fs-texture2drect).
And a couple stop rendering correctly (glsl-fs-bug25902).

v2: Move the attribute format setup in the key from after search time to
    before the search.
v3: Fix reading of attributes other than position (I forgot to respect
    attr and stored everything in inputs 0-3, i.e. position).
2014-08-08 18:59:47 -07:00
Eric Anholt
f069367f39 vc4: Add support for the TGSI FRC opcode.
v2: Rebase on helpers.
2014-08-08 18:59:47 -07:00
Eric Anholt
bf542cd372 vc4: Add support for the TGSI TRUNC opcode.
v2: Rebase on helpers.
2014-08-08 18:59:47 -07:00
Eric Anholt
399285403a vc4: Crank up the tile allocation BO size
This avoids a simulator assertion failure with glamor.  I need to actually
support resize, though.
2014-08-08 18:59:47 -07:00
Eric Anholt
75afa64ef8 vc4: Add support for multiple attributes 2014-08-08 18:59:47 -07:00
Eric Anholt
32948ca768 vc4: Add more useful debug for the undefined-source case
We could get undefined sources in real programs from the wild, so we'll
need to turn off this debug eventually.  But for now, using undefined
sources is typically me just mistyping something.
2014-08-08 18:59:47 -07:00
Eric Anholt
6ff2129d58 vc4: Add support for the lit opcode.
v2: Fix how it was using the X channel for the real work of the opcode,
    instead of Y.  Fixes glean's LIT test.
v3: Rebase on the helpers.
2014-08-08 18:59:47 -07:00
Eric Anholt
63e49da0a5 vc4: Add support for the POW opcode
v2: Rebase on helpers.
2014-08-08 18:59:47 -07:00
Eric Anholt
0e182e7d8f vc4: Refactor uniform handling.
I wanted an easy way to set up new uniforms every time, so I could handle
texture-sampler-related uniforms.

v2: Rebase on helpers change.
2014-08-08 18:59:47 -07:00