Commit graph

92185 commits

Author SHA1 Message Date
Jason Ekstrand
d9df82f2ff isl: Add helpers for creating different types of aux surfaces
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
3c44d99653 i965/miptree: Use mcs_mt->qpitch for aux surfaces
At one point, we were doing this correctly.  It must have gotten lost in
one of the many rebases.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
67ea60db0b i965/miptree: Allow get_aux_isl_surf when there is no aux surface
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
dd46c8da31 i965/miptree: Support depth in get_isl_clear_color
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
6155d4ef56 isl/state: Add an assertion for IVB multisample array textures
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
3c75b315e1 isl: Add a #define for DEV_IS_BAYTRAIL
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
56746d04d5 i965/blorp: Remove unused fields from blorp_surface_info
The only reason why we need layer or level is that we need the z-offset for
3-D surfaces.  Let's just have the one field for that.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
1495b6315e i965/blorp: Simplify depth buffer state setup a bit
The data comes in via ISL in a format that's almost directly usable by the
hardware so we can avoid some of the conversion headache.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
d814353365 i965/blorp: Use the generic surface state path for gen8 textures
Now that the generic blorp path uses base level/layer, there's no need to
make gen8 special.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
ed432fd681 isl: Add asserts for gen8+ X/YOffset rules
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
96fa98c18e i965/blorp: Only do offset hacks for fake W-tiling and IMS
Since the dawn of time, blorp has used offsets directly to get at different
mip levels and array slices of surfaces.  This isn't really necessary since
we can just use the base level/layer provided in the surface state.  While
it may have simplified blorp's original design, we haven't been using the
blorp path for surface state on gen8 thanks to render compression and
there's really no good need for it most of the time.  This commit restricts
such surface munging to the cases of fake W-tiling and fake interleaved
multisampling.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
9f9abc8214 i965/blorp: Add a z_offset field to blorp_surface_info
The layer field is in terms of physical layers which isn't quite what the
sampler will want for 2-D MS array textures.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
a9a6df807e i965/blorp: Pass the Z component into all texture operations
Multisample array surfaces on IVB don't support the minimum array element
surface attribute so it needs to come through the sampler message.  We may
as well just pass it through everything.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
7abcdfbe13 i965/blorp: Rework hiz rect alignment calculations
At the moment, the minify operation does nothing because
params.depth.view.base_level is always zero.  However, as soon as we start
using actual base miplevels and array slices, we are going to need the
minification.  Also, we only need to align the surface dimensions in the
case where we are operating on miplevel 0.  Previously, it didn't matter
because it aligned on miplevel 0 and, for all other miplevels, the miptree
code guaranteed that the level was already aligned.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
871893cda2 i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on gen9
The sampling hardware can handle them ok.  It just looks at the tiling to
determine whether it's the new gen9 1-D layout or the old one.  The render
hardware isn't so smart.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
ecd9789368 i965/miptree: Fill out the isl_surf::usage field
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
560a92c4fd isl: Take the slice0_extent shortcut for interleaved MSAA
The shortcut works just fine for MSAA and the comment even says so.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
1e02611276 isl: Remove duplicate px->sa conversions
In all three cases, we start with width and height taken from
isl_surf::phys_slice0_extent_sa which is already in samples.  There is no
need to do the conversion and doing so gives us an incorrect value.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
603d5f7638 i965/blorp: Use the isl_view from the blorp_surface_info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
c097160463 i965/blorp: Get rid of brw_blorp_surface_info::width/height
Instead, we manually mutate the surface size as needed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
2095f932ef i965/blorp: Move surface offset calculations into a helper
The helper does a full transformation on the surface to turn it into a new
2-D single-layer single-level surface representing the original layer and
level in memory.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
90ab43d1bb i965/blorp: Use ISL to compute image offsets
For the moment, we still call the old miptree function; we just assert that
the two are equal.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
ba88a9622d isl: Add functions for computing surface offsets in samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
f6c75df083 isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces
The function takes a logical array layer but was assuming it was a physical
array layer.  While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
7997f4f95b i965/blorp: Add an isl_view to blorp_surface_info
Eventually, this will be the actual view that gets passed into isl to
create the surface state.  For now, we just use it for the format and the
swizzle.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
e046a46460 i965/blorp: Move intratile offset calculations out of surface state setup
Previously we multiplied full x/y offsets, resolved tile aligned buffer
offset and intra tile offset based on that.  Now we let ISL to take into
account the msaa setting and we only multiply the resolved intra tile
offsets.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
27a58615d3 i965/blorp: Refactor interleaved multisample destination handling
We put all of the code for fake IMS together.  This requires moving a bit
of the program key setup code further down so that it gets the right values
out of the final surface.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
3c25caa318 i965/blorp: Get rid of brw_blorp_surface_info::array_layout
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
09879eff30 i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout
We also remove brw_blorp_surface_info::msaa_layout.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
e2a1bdb3c5 i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetch
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
28b0ad890c i965/blorp: Get rid of brw_blorp_surface_info::num_samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
aa6c058ac4 i965/blorp: Make sample count asserts a bit more lazy
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
aa4117a9e4 i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled
Now that we're carrying around the isl_surf, we can just modify it
directly instead of passing an extra bit around.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
801189e199 i965/blorp: Remove compute_tile_offsets
We have a handy little function is ISL that does exactly the same thing.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
b82de88008 i965/blorp: Create the isl_surf up-front
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
ffeb5f67ac i965/blorp/clear: Initialize surface info after allocating an MCS
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
1666d029aa isl/state: Use a valid alignment for 1-D textures
The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
0aa0b39769 i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masks
It's only used to stomp the tiling to Y and it's only used by blorp so
there's no reason why blorp can't do it itself.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
573f6ffd04 isl: Fix the parameter names for get_intratile_offset
It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Brian Paul
5de29aeef0 util: try to use SSE instructions with MSVC and 32-bit gcc
The lrint() and lrintf() functions are pretty slow and make some
texture transfers very inefficient.  This patch makes a better effort
at using those intrisics for 32-bit gcc and MSVC.

Note, this patch doesn't address the use of SSE4.1 with MSVC.

v2: get rid of the ROUND_WITH_SSE symbol, per Matt.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-17 12:53:20 -06:00
Brian Paul
18e6e0796a svga: fix src/dst typo in can_blit_via_copy_region_vgpu10()
The function was always returning false because of this typo.

Retested with piglit.  There's some sRGB-related blit failures, but
that seems unrelated.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
2016-08-17 12:53:20 -06:00
Brian Paul
55417140cd svga: initialize a variable to silence a gcc warning
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-08-17 12:53:20 -06:00
Ian Romanick
607ab6d3bf glsl: Pull enum ir_expression_operation out to its own file
No change except to the copyright symbol.  The next patch will generate
this file with Python, and Unicode + Python = pure rage.

v2: Massive rebase... I guess a lot can change in a year.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-17 13:48:25 +01:00
Ian Romanick
de71bc9eb6 glsl: Make the generated sources build rules more like NIR
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-17 13:48:25 +01:00
Francesco Ansanelli
120c9c6380 mesa/st: use llabs instead of abs for long args (v2)
v2: long has 32bit on Windows (Marek)
Signed-off-by: Francesco Ansanelli <francians@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-08-17 14:16:29 +02:00
Marek Olšák
57a8991020 radeonsi: fix up buffer descriptor upper-bound checking
st/mesa does this too, so we're safe.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 14:15:33 +02:00
Marek Olšák
325379096f gallium: change pipe_image_view::first_element/last_element -> offset/size
This is required by OpenGL. Our hardware supports this.

Example: Bind RGBA32F with offset = 4 bytes.

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 14:15:33 +02:00
Marek Olšák
7cd256ce7e gallium: change pipe_sampler_view::first_element/last_element -> offset/size
This is required by OpenGL. Our hardware supports this.

Example: Bind RGBA32F with offset = 4 bytes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97305

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 14:15:33 +02:00
Marek Olšák
1ac23a9359 gallium/radeon: assign the highest priority to scratch; make rings second
just FYI, the kernel receives priority/4

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 14:15:29 +02:00
Marek Olšák
9009516501 gallium/winsys: re-number winsys priority flags
free 60..63, move CP_DMA up

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-17 12:24:35 +02:00