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Author SHA1 Message Date
Georg Lehmann
809fb0fba3 ac/nir/lower_ps_late: emit scalar f2f16_rtz for when one half of a packed export is undef 
Foz-DB Navi48:
Totals from 7200 (8.74% of 82405) affected shaders:
Instrs: 9056391 -> 9048177 (-0.09%); split: -0.09%, +0.00%
CodeSize: 48681288 -> 48640684 (-0.08%); split: -0.09%, +0.00%
VGPRs: 413088 -> 413784 (+0.17%)
Latency: 76340711 -> 76320080 (-0.03%); split: -0.03%, +0.00%
InvThroughput: 12692959 -> 12684618 (-0.07%); split: -0.07%, +0.00%
VClause: 148823 -> 148821 (-0.00%)
Copies: 601739 -> 601874 (+0.02%); split: -0.01%, +0.03%
VALU: 5213356 -> 5207253 (-0.12%); split: -0.12%, +0.00%
SALU: 1160815 -> 1160817 (+0.00%); split: -0.00%, +0.00%
VOPD: 79520 -> 79444 (-0.10%); split: +0.09%, -0.18%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:23 +00:00
Georg Lehmann
8c895c5c61 ac/nir/lower_ps_late: CSE partial packed exports 
Foz-DB Navi48:
Totals from 425 (0.52% of 82405) affected shaders:
Instrs: 1110029 -> 1109658 (-0.03%); split: -0.03%, +0.00%
CodeSize: 6135272 -> 6133848 (-0.02%); split: -0.02%, +0.00%
VGPRs: 29856 -> 29844 (-0.04%)
Latency: 10258411 -> 10258043 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 1898177 -> 1897661 (-0.03%)
Copies: 88221 -> 88173 (-0.05%)
VALU: 575276 -> 574894 (-0.07%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:22 +00:00
Georg Lehmann
e74323577f aco/optimizer: optimize pack(undef, f2f16_rtz(a)) for salu 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:22 +00:00
Georg Lehmann
6cbd16daae aco/optimizer: optimize pack(undef, f2f16_rtz(a)) for gfx8+ 
Do this late because the v_cvt_pkrtz_f16_f32 can be applied to
its operand.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:22 +00:00
Georg Lehmann
57ca974d1d aco/optimizer: optimize pack(undef, f2f16_rtz(a)) for gfx6/7 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:21 +00:00
Georg Lehmann
ba73792de0 aco/optimizer: fix parsing salu p_insert as shift 
Fixes: 88f7e3fff3 ("aco/optimizer: parse pseudo alu instructions")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:21 +00:00
Georg Lehmann
830d6de9ff aco/isel: optimize pack_32_2x16_split(undef, const) 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:20 +00:00
Georg Lehmann
b2d9615000 nir/opt_algebraic: optimize bcsel to hi 16bits with undef lo 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:20 +00:00
Georg Lehmann
d06b627d23 nir/opt_algebraic: optimize f2f16_rtz of bcsel with constants 
Foz-DB Navi48:
Totals from 145 (0.18% of 82405) affected shaders:
Instrs: 1706001 -> 1705669 (-0.02%); split: -0.03%, +0.01%
CodeSize: 9621036 -> 9620784 (-0.00%); split: -0.02%, +0.02%
SpillSGPRs: 711 -> 726 (+2.11%); split: -0.56%, +2.67%
Latency: 20066360 -> 20066193 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 4326789 -> 4326763 (-0.00%); split: -0.00%, +0.00%
Copies: 192041 -> 191995 (-0.02%); split: -0.03%, +0.01%
Branches: 75673 -> 75675 (+0.00%); split: -0.00%, +0.01%
VALU: 765163 -> 764835 (-0.04%); split: -0.05%, +0.00%
SALU: 351758 -> 351715 (-0.01%); split: -0.01%, +0.00%
VOPD: 65236 -> 65282 (+0.07%); split: +0.17%, -0.10%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:20 +00:00
Georg Lehmann
ee5492e6dd nir/opt_algebraic: remove f2f16 roundtrip conversions 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:20 +00:00
Georg Lehmann
592b6579da nir/opt_algebraic: optimize f2f16_rtz(min/max) 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:18 +00:00
Georg Lehmann
2b92c0f06e nir/opt_algebraic: optimize f2f16_rtz(b2f(a)) 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:18 +00:00
Danylo Piliaiev
096e0aae74 tu: Avoid disabling LRZ when possible for suspend/resume+depth-only draws
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We don't actually care if previous suspended RP had depth-only draws
with color writes skipped, we only care if previous RP disabled LRZ
writes due to this; the mere fact of first draws being depth-only
doesn't affect LRZ of next draws in any way.

However, for next RPs in suspend-resume chain we have to assume that
previous RP may have had color writes.

For secondary cmdbufs with ordinary renderpasses it is easy to be
less pessimistic, and that's what we do in order to not regress
DXVK performance.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39293>
 2026-01-26 09:48:44 +00:00
Rhys Perry
928ecfc6c0 radv: fix RADV_DEBUG=shaderstats with RT pipelines 
radv_dump_shader_stats() printed stats for every shader with a certain
stage, and we called this function each time an RT shader is compiled.

This means we could repeat the stats for a shader.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39484>
 2026-01-26 09:26:14 +00:00
Rhys Perry
e59a0df302 aco/insert_fp_mode: remove incorrect assertion 
This can happen if a loop has no continues, and the later code should work
fine in this situation.

This fixes war_thunder/0013a69e097b2471 on navi21.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 6b9d28ab9b ("aco/insert_fp_mode: insert fp mode in reverse")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39481>
 2026-01-26 08:57:33 +00:00
Samuel Pitoiset
c91ed27582 radv: use the SQTT enable bit for PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39425>
 2026-01-26 08:10:53 +00:00
Samuel Pitoiset
e272c8062d radv: use the SQTT enable bit for PKT3_DISPATCH_MESH_INDIRECT_MULTI 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39425>
 2026-01-26 08:10:53 +00:00
Samuel Pitoiset
c7da19e2bf radv: use the SQTT enable bit for PKT3_DRAW_{INDEX}_INDIRECT_MULTI 
This reports more info in RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39425>
 2026-01-26 08:10:52 +00:00
Samuel Pitoiset
e5982496f6 radv: move emitting SQTT markers closer to the draw/dispatch packets 
Some packets already include a SQTT enable bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39425>
 2026-01-26 08:10:52 +00:00
Wei Zhao
a8272bf0f1 vulkan/wsi/wayland: use roundtrip instead of flush on swapchain free 
Use wl_display_roundtrip() instead of wl_display_flush() when freeing
a swapchain to ensure the compositor has processed buffer release
events before continuing.

wl_display_flush() only sends pending requests without waiting for
the compositor to process them. When rapidly creating and destroying
large swapchain buffers, buffer references may not be released quickly
enough (e.g., during CTS testing), causing memory to accumulate.

Using wl_display_roundtrip() ensures synchronization with the
compositor, allowing buffers to be released promptly.

Signed-off-by: Wei Zhao <Wei.Zhao@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39475>
 2026-01-26 06:27:37 +00:00
Emma Anholt
feb3e8f46e nir/opt_algebraic_tests: Initialize an obvious dummy value for all defs.
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We were initializing to a nir_const_value of undefined (in practice on x86
builds, a pointer value), with .b set to 0.  Those values would get dumped
in the annotated shader disassembly at the end of a test where all inputs
where unexpectedly skipped, producing very surprising output.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:42 +00:00
Emma Anholt
6b6cf7b89f nir/opt_algebraic_tests: Fix annotating uint values. 
In debugging the CI flakes, it was disconcerting to see:

1     %1 = fisnormal %0 (0.000000) // 0x55e7c4147c00

instead of:

1     %1 = fisnormal %0 (0.000000) // 0x0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:42 +00:00
Emma Anholt
77cfb20d0a nir/opt_algebraic_tests: Fix leak of the variable conds ht. 
We'd end the test with 500MB leaked.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:42 +00:00
Emma Anholt
cdec063d37 nir/opt_algebraic: Fix a bit of imad24_ir3's optimization. 
The mul is 24-bit sign-extended, so in simplifying we should retain that.
If nothing else, this keeps us on the happy path of mul24s.

I didn't fix the other broken pattern, since it's not really part of this
MR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:41 +00:00
Emma Anholt
e5a9eae2b5 nir/opt_algebraic_tests: Fix fuzzing levels for multi-component inputs. 
We were enumerating enough for a single component, but not all the
combinations.  This helps show that our fdots fail pretty consistently.
And triggers more skipping from the fany_equal16s thanks to varied inputs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:41 +00:00
Emma Anholt
7fd0287a89 nir/opt_algebraic_tests: Test !nir_fp_preserve_signed_zero behavior. 
Iterate over a set of sign-flips for 0.0s to see if we can find a set that
makes the search and replace sides match.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:41 +00:00
Emma Anholt
d9eb9a3eef nir/opt_algebraic_tests: Make sure we test the same inputs on BE as LE. 
With the inexact signed zero support, we ended up with diverging inputs
producing diverging "all skipped" results for the matrix mul tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
68f5bc4f12 nir/opt_algebraic_tests: Rename and use the enum result type more. 
As I introduced another layer of iteration for signed zero testing, the
former logic got unwieldy.  In fact, it was already unwieldy enough that I
forgot to clear all_skipped when the assert failed, allowing a failing
test to be marked UNSUPPORTED instead of XFAIL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
7f1a64e7f5 nir/opt_algebraic_tests: Move more of the base class code to be methods. 
Less passing the *test around separately.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
845e2b3954 nir/opt_algebraic_tests: Remove unnecessary input_count. 
Originally this was for sizing the array, but now we're doing std::vector.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
a90163a15a nir/opt_algebraic_tests: Add support for expression swizzles. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
c30c383d4d nir/opt_algebraic_tests: Allow testing of fdot*_replicated opcodes. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
173295adf4 nir/opt_algebraic_tests: Allow testing udiv_aligned_4. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
231a477402 nir/opcodes: Define udiv_aligned_4 to return poison for not-aligned-4. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
94237c3ea3 nir/opt_algebraic_tests: Allow testing mul/mad_relaxed opcodes. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
f82621bfdc nir/opcodes: Define the mul/mad_relaxed opcodes to return poison for OOB. 
For the "defined results for >24b", you want the non-relaxed opcodes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:39 +00:00
Emma Anholt
fd7754fba1 nir/opt_algebraic_tests: Allow testing imad24_ir3. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:39 +00:00
Emma Anholt
ce7ad2639a nir: Fix C UB in imad24_ir3 evaluation. 
Same fix as imul24, technically you can't shift into the top bit of the
int32, but the util helper does it right.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:39 +00:00
Alyssa Rosenzweig
5409d872f7 brw: remove a redundant DCE 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39513>
 2026-01-25 17:17:06 -08:00
Alyssa Rosenzweig
5fe71dc717 brw: combine more peephole select 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39513>
 2026-01-25 17:17:06 -08:00
Alyssa Rosenzweig
b34806e357 brw: optimize bfi only late 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39513>
 2026-01-25 17:17:06 -08:00
Alyssa Rosenzweig
c45c5440cd brw: run nir_opt_idiv_const only once 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39513>
 2026-01-25 16:17:30 -08:00
Alyssa Rosenzweig
a8b78e5a8c brw: only optimize ray queries if there are any 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39513>
 2026-01-25 16:17:30 -08:00
Alyssa Rosenzweig
7078496efe brw: only optimize ray queries once 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39513>
 2026-01-25 16:17:30 -08:00
Alyssa Rosenzweig
99d22bc35e brw: run opt_deref only once 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39513>
 2026-01-25 16:17:30 -08:00
Alyssa Rosenzweig
73fa431bff brw: unloop post-mem vectorize opts
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There's enough looping happening elsewhere for it to not really matter.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39514>
 2026-01-25 23:41:41 +00:00
Alyssa Rosenzweig
11dba60e6e brw: hoist lower_pack OOTL 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39514>
 2026-01-25 23:41:41 +00:00
Alyssa Rosenzweig
3cfc431fb2 brw: remove redundant nir_opt_combine_stores 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39514>
 2026-01-25 23:41:40 +00:00
Alyssa Rosenzweig
ced1adcad7 brw: move nir_opt_memcpy OOTL 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39514>
 2026-01-25 23:41:40 +00:00
Zan Dobersek
5a3b0ce461 tu: avoid incorrect pipeline draw state for disabled depth/stencil attachments
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Pipeline creation can generate draw state that will, depending on creation
state, assume enabled depth and stencil attachments. Later on, the pipeline
can be used in a render pass that disables those attachments, while the
draw state will still be emitting as if those attachments are present and
usable. Specifically, this affects pairings of depth attachments and
TU_DYNAMIC_STATE_RB_DEPTH_CNTL, and of stencil attachments and
TU_DYNAMIC_STATE_DS.

When a pipeline is bound, ignore its set depth/stencil state if that state
was enabled and the pipeline is either bound outside of a render pass or
inside a render pass that disables the relevant attachment. This way the
depth/stencil state will be treated as dynamic and will be recomputed and
emitted during the draw state emission, taking into account the available
attachments inside the render pass.

Fixes: dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39323>
 2026-01-25 09:30:05 +00:00