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99250 commits

Author SHA1 Message Date
Iago Toral Quiroga
7ec6e4e689 anv/query: implement multiview interactions
From the Vulkan spec with KHX extensions:

  "If queries are used while executing a render pass instance that has
   multiview enabled, the query uses N consecutive query indices
   in the query pool (starting at query) where N is the number of bits
   set in the view mask in the subpass the query is used in.

   How the numerical results of the query are distributed among the
   queries is implementation-dependent. For example, some implementations
   may write each view's results to a distinct query, while other
   implementations may write the total result to the first query and write
   zero to the other queries. However, the sum of the results in all the
   queries must accurately reflect the total result of the query summed
   over all views. Applications can sum the results from all the queries to
   compute the total result."

In our case we only really emit a single query (in the first query index)
that stores the aggregated result for all views, but we still need to manage
availability for all the other query indices involved, even if we don't
actually use them.

This is relevant when clients call vkGetQueryPoolResults and pass all N
queries to retrieve the results. In that scenario, without this patch,
we will never see queries other than the first being available since we
never emit them.

v2: we need the same treatment for timestamp queries.

v3 (Jason):
 - Better an if instead of an early return.
 - We can't write to this memory in the CPU, we should use
   MI_STORE_DATA_IMM and emit_query_availability (Jason).

v4 (Jason):
 - No need to take the value to write as parameter, just hard code it to 0.

Fixes test failures in some work-in-progress CTS multiview+query tests.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-01-18 16:37:06 +01:00
Emil Velikov
c9b2cb7897 vc5: add missing files to the tarball
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-18 11:36:36 +00:00
Emil Velikov
393cf04fa4 broadcom: add missing headers to the tarball
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-18 11:21:35 +00:00
Mario Kleiner
d67ef48580 i965/screen: Allow drirc to set 'allow_rgb10_configs' again.
Since setup of ALLOW_RGB10_CONFIGS was moved to i965's own
brw_config_options.xml, this was hard-coded to false and
could not be overriden by drirc. Add some parsing into
i965's private screen->optionCache to enable drirc again.

Fixes: b391fb26df ("dri_util: remove ALLOW_RGB10_CONFIGS option (v2)")
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-01-18 08:18:47 +02:00
Samuel Iglesias Gonsálvez
eac629deb6 anv: return VK_ERROR_OUT_OF_DEVICE_MEMORY when surface size is out of HW limits
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-01-18 06:48:47 +01:00
Timothy Arceri
9248f72c4e ac: tidy up array indexing logic
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-18 15:59:27 +11:00
Rob Clark
4c69961daf mesa/st: translate SO info in glsl_to_nir() case
This was handled for VS, but not for GS.

Fixes for gallium drivers using nir:
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams*
spec@arb_transform_feedback3@arb_transform_feedback3-ext_interleaved_two_bufs_gs*
spec@ext_transform_feedback@geometry-shaders-basic
spec@ext_transform_feedback@* use_gs
spec@glsl-1.50@execution@geometry@primitive-id*
spec@glsl-1.50@execution@geometry@tri-strip-ordering-with-prim-restart gl_triangle_strip *
spec@glsl-1.50@transform-feedback-builtins
spec@glsl-1.50@transform-feedback-type-and-size

v2: don't call st_translate_program_stream_output) for TCS

v3: drop scanning patch outputs as TCS can't output xfb

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
2018-01-18 15:35:58 +11:00
Dave Airlie
44a27cdcec r600/sb: add lds related peepholes.
if no destination:
a) convert _RET instructions to non _RET variants if no dst
b) set src0 to undefined if it's a READ, this should get DCE then.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:38:17 +00:00
Dave Airlie
3bb2b2cc45 r600/sb: use different stacks for tracking lds and queue usage.
The normal ssa renumbering isn't sufficient for LDS queue access,
this uses two stacks, one for the lds queue, and one for the
lds r/w ordering.

The LDS oq values are incremented in their use in a linear
fashion.
The LDS rw values are incremented in their definitions and used
in the next lds operation to ensure reordering doesn't occur.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:38:09 +00:00
Dave Airlie
8cfec333c0 r600/sb: schedule LDS ops in appropriate places.
So LDS ops have to be SLOT_X,
and LDS OQ reads have read port restrictions so we try
and force those into only having one per slot and avoiding
bank swizzles.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:38:05 +00:00
Dave Airlie
71a50de4fc r600/sb: hit the scheduler with a big hammer to avoid lds splits.
This tries to avoid an lds queue read getting scheduled separately
from an lds ret read, the non-sb code uses the same style of hammer,
this isn't foolproof.

We can do better, but it's a bit tricky, as you have to scan ahead
and either schedule more lds oq moves and more lds reads and that
could lead to you running out of space anyways.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:37:56 +00:00
Dave Airlie
46549bd6b6 r600/sb: adding lds oq tracking to the scheduler
This adds support for tracking the lds oq read/writes
so can avoid scheduling other things in between.

This patch just adds the tracking and assert to show
problems.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:37:52 +00:00
Dave Airlie
5002dd4052 r600/sb: add gcm support to avoid clause between lds read/queue read
You have to schedule LDS_READ_RET _, x and MOV reg, LDS_OQ_A_POP
in the same basic block/clause. This makes sure once we've issues
and MOV we don't add another block until we balance it with an
LDS read.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:37:42 +00:00
Dave Airlie
046cf68cad r600/sb: handle lds special dest registers.
This adds lds to the geom emit handling

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:37:39 +00:00
Dave Airlie
d72590032f r600/sb: handle LDS operations in folding.
Don't try and fold LDS using expressions.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:37:35 +00:00
Dave Airlie
c314b0a27a r600/sb: add finalising for lds output queue special values.
We need to convert these to the hw special registers.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:37:27 +00:00
Dave Airlie
9f3a1e9b0c r600/sb: add initial support for parsing lds operations.
This handles parsing the LDS ops and queue accessess.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:37:13 +00:00
Dave Airlie
795512b235 r600/sb: disable if conversion for hs
This fixes bad interactions with the LDS special values.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:37:01 +00:00
Dave Airlie
1ca2eb3bf3 r600/sb: lds ops have no dst register.
Although these are op3s they don't have a dst reg.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:36:52 +00:00
Dave Airlie
09c1c13c44 r600/sb: introduce special register values for lds support.
For LDS read/write ordering we use the LDS_RW value, reads
will wait on previous writes.
For LDS read/read from LDS queue ordering we use the LDS_OQ
values, we define two for now, though initially we'll just
support OQA.

Also add the check for the lds oq values

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:36:47 +00:00
Dave Airlie
2f2cef385f r600/sb: update last_cf if alu is the last clause
It's rare to have a final alu clause on normal shaders (exports)
but tess shaders write to LDS as their output, so we see some
alu clauses, and the CF_END get put in the wrong place.

This makes sure to update last_cf correctly.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:36:41 +00:00
Dave Airlie
da977ad907 r600/sb: start adding GDS support
This adds support for GDS ops to sb backend.

This seems to work for atomics and tess factor writes.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:35:37 +00:00
Dave Airlie
05f5282d63 r600/sb: add tess/compute initial state registers.
This stops them being optimised out.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:35:12 +00:00
Dave Airlie
68b976bd91 r600/sb: fix a bug emitting ar load from a constant.
Some tess shaders were doing MOVA_INT _, c0.x on cayman, and then
hitting an assert in sb_bc_finalize.cpp:translate_kcache.

This makes sure the toplevel kcache tracker gets updated,
and the clause gets fixed up.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:34:46 +00:00
Dave Airlie
7efcafce7c r600/shader: only emit add instruction if param has a value.
Just saves a pointless a = a + 0;

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:34:43 +00:00
Dave Airlie
2bd01adf14 r600: emit 0 gds_op for tf write.
This field is ignored for tf writes so should be 0.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 03:34:36 +00:00
Dave Airlie
9041730d1c r600: add support for ARB_shader_clock.
Reviewed-by: Gert Wollny <gw.fossedev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 13:25:59 +10:00
Dave Airlie
6785034a70 radv/ws: get rid of useless return value
This also used boolean, so nice to kill that.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-01-18 01:57:53 +00:00
Bas Nieuwenhuizen
2ce11ac11f radv: Initialize DCC on transition from preinitialized.
Looks like the decompress does not handle invalid encodings well,
which happens with random memory. Of course apps should not use it
with random memory, but they are allowed to ....

Fixes: 44fcf58744 "radv: Disable DCC for GENERAL layout and compute transfer dest."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-18 01:57:52 +01:00
Timothy Arceri
e2b9296146 ac: fix buffer overflow bug in 64bit SSBO loads
Fixes: 441ee1e65b "radv/ac: Implement Float64 SSBO loads"

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-18 10:26:58 +11:00
Timothy Arceri
409e15f26f ac: fix nir_intrinsic_get_buffer_size for radeonsi
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-18 10:25:20 +11:00
Kenneth Graunke
d139b5e4cc i965: Pass brw_growing_bo to grow_buffer().
Cleaner.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-01-17 13:13:26 -08:00
Kenneth Graunke
81ca8e69e3 i965: Make a helper for recreating growing buffers.
Now that we have two of these, we're duplicating a bunch of this logic.
The next commit will add more logic, which would make the duplication
seem worse.

This ends up setting EXEC_OBJECT_CAPTURE on the batch, which isn't
necessary (it's already captured), but it should be harmless.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-01-17 13:13:26 -08:00
Kenneth Graunke
02c1c25b1a i965: Replace cpu_map pointers with a "use_shadow_copy" boolean.
Having a boolean for "we're using malloc'd shadow copies for all
buffers" is cleaner than having a cpu_map pointer for each.  It was
okay when we had one buffer, but this is more obvious.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-01-17 13:13:26 -08:00
Francisco Jerez
11674dad8a intel/fs: Optimize and simplify the copy propagation dataflow logic.
Previously the dataflow propagation algorithm would calculate the ACP
live-in and -out sets in a two-pass fixed-point algorithm.  The first
pass would update the live-out sets of all basic blocks of the program
based on their live-in sets, while the second pass would update the
live-in sets based on the live-out sets.  This is incredibly
inefficient in the typical case where the CFG of the program is
approximately acyclic, because it can take up to 2*n passes for an ACP
entry introduced at the top of the program to reach the bottom (where
n is the number of basic blocks in the program), until which point the
algorithm won't be able to reach a fixed point.

The same effect can be achieved in a single pass by computing the
live-in and -out sets in lock-step, because that makes sure that
processing of any basic block will pick up the updated live-out sets
of the lexically preceding blocks.  This gives the dataflow
propagation algorithm effectively O(n) run-time instead of O(n^2) in
the acyclic case.

The time spent in dataflow propagation is reduced by 30x in the
GLES31.functional.ssbo.layout.random.all_shared_buffer.5 dEQP
test-case on my CHV system (the improvement is likely to be of the
same order of magnitude on other platforms).  This more than reverses
an apparent run-time regression in this test-case from my previous
copy-propagation undefined-value handling patch, which was ultimately
caused by the additional work introduced in that commit to account for
undefined values being multiplied by a huge quadratic factor.

According to Chad this test was failing on CHV due to a 30s time-out
imposed by the Android CTS (this was the case regardless of my
undefined-value handling patch, even though my patch substantially
exacerbated the issue).  On my CHV system this patch reduces the
overall run-time of the test by approximately 12x, getting us to
around 13s, well below the time-out.

v2: Initialize live-out set to the universal set to avoid rather
    pessimistic dataflow estimation in shaders with cycles (Addresses
    performance regression reported by Eero in GpuTest Piano).
    Performance numbers given above still apply.  No shader-db changes
    with respect to master.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104271
Reported-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-17 11:56:08 -08:00
Marek Olšák
63b231309e gallium: remove PIPE_CAP_USER_CONSTANT_BUFFERS
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-01-17 20:18:00 +01:00
Marek Olšák
85bbcdda34 st/mesa: assume that user constant buffers are always supported
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-01-17 20:17:59 +01:00
Marek Olšák
5981a5226e nine: assume that user constant buffers are always supported
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-01-17 20:17:59 +01:00
Marek Olšák
e871abe452 gallium: remove PIPE_CAP_TEXTURE_SHADOW_MAP
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-01-17 20:17:59 +01:00
Marek Olšák
e411d2572b st/mesa: expose ARB_sync unconditionally
All drivers support it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-01-17 20:17:59 +01:00
Marek Olšák
3778a0a533 gallium: remove PIPE_CAP_TWO_SIDED_STENCIL
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-01-17 20:17:59 +01:00
Brian Paul
f631a6ae8c glsl: remove unneeded extern "C" {} bracketing around Mesa includes
The two headers already have the right extern "C" annotations.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00
Brian Paul
7421e34dd6 mesa: move gl_external_samplers() to program.[ch]
The function is only called from a couple places.  It doesn't make
sense to have it in mtypes.h

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00
Brian Paul
6dc8896726 st/mesa: include util/bitscan.h in st_glsl_to_tgsi_temprename.cpp
And use "" instead of <> for including Mesa headers, as we do elsewhere.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00
Brian Paul
741d423478 glsl: include util/bitscan.h in serialize.cpp
Instead of relying on indirect inclusion of the header.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00
Brian Paul
2f14146200 util: include string.h in u_dynarray.h
To get memset() prototype.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00
Brian Paul
02c0734adc mesa: remove unneeded #includes of main/compiler.h
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00
Brian Paul
7845397183 st/mesa: remove unneeded #includes of main/compiler.h
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00
Brian Paul
bafa33befd st/mesa: include main/compiler.h in st_cb_queryobj.c
To get CPU_TO_LE32() macro.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00
Brian Paul
7de0262f8f mesa: include util/macros.h in format_fallback.c
To get definition of unreachable() macro.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-01-17 11:17:56 -07:00