Commit graph

4569 commits

Author SHA1 Message Date
Marcin Ślusarz
7ebfbc97a8 nir: use wg id to wg idx shortcut if two dims of num_workgroups are 1
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22334>
2023-07-04 09:15:07 +00:00
Marcin Ślusarz
b5792c1a34 nir: extract try_lower_id_to_index_1d
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22334>
2023-07-04 09:15:07 +00:00
Caio Oliveira
608504c774 nir/print: Reformat the preds/succs block information
- Always print preds in same line as block name;
- Use a single line for empty blocks;
- Align preds/succs with the instructions.

```
if %29 {
    block b4:    // preds: b3
    32     %30 = load_const (0x00000000 = 0.000000)
    32x4   %31 = @vulkan_resource_index (%30 (0x0)) (desc_set=0, binding=0, desc_type=SSBO)
    32x4   %32 = @load_vulkan_descriptor (%31) (desc_type=SSBO)
    32x4   %33 = deref_cast (Storage *)%32 (ssbo Storage)  (ptr_stride=0, align_mul=4, align_offset=0)
    32x4   %34 = deref_struct &%33->fail (ssbo uint)  // &((Storage *)%32)->fail
    32     %36 = @deref_atomic (%34, %35 (0x1)) (access=1, atomic_op=iadd)
                 // succs: b6
} else {
    block b5:  // preds: b3, succs: b6
}
```

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:07 +00:00
Caio Oliveira
a188337972 nir/print: Print div/con annotation first
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:07 +00:00
Caio Oliveira
884debdee3 nir/print: Use 4-space indentation
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:06 +00:00
Caio Oliveira
9215aad7da nir/print: Use // for comments
Makes it easier to copy snippets of shaders into code or
test comments without worrying about conflict with `/* */`.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:06 +00:00
Caio Oliveira
1c0038d5d5 nir/print: Don't use comment syntax for deref_cast properties
Follow the same syntax as the intrinsic indices, since they
are conceptually similar.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:06 +00:00
Caio Oliveira
88c411c638 nir/print: Rename print_tabs() to print_indentation() and use it more
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:06 +00:00
Caio Oliveira
761d90341f nir/print: Align instructions around =
- For SSA destination, padding is applied before `%`.
- For Reg destination, pad to the SSA size (to align div/con),
  then remaining padding is applied before `r`.
- For instructions without destination, padding is applied so
  they start right after the ` = ` of the cases above.

If the block doesn't have any destinations, there's no padding
is applied to the instructions without destinations in that
block.

For now registers with array access will be unaligned.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:06 +00:00
Caio Oliveira
58e3abc4a3 nir/print: Use BITSIZExELEMENTS for SSA sizes
Omits the `x1` part if its one element.

```
32x3   %3 = @load_deref (%0) (access=0)
32     %4 = mov %3.x
32     %5 = deref_var &gl_LocalInvocationID (system uvec3)
32x3   %8 = @load_deref (%5) (access=0)
32     %9 = mov %8.x
```

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:06 +00:00
Caio Oliveira
252a6140ea nir/print: Use bN instead of block_N for identifying basic blocks
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:06 +00:00
Caio Oliveira
ea44879d2d nir/print: Use symbols % for SSA and @ for intrinsic
The variable uniquifying now uses # instead of @.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23564>
2023-07-03 22:18:06 +00:00
Yonggang Luo
c4d3bc03c4 nir: Add nir_foreach_function_safe and use it
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23902>
2023-07-03 21:45:35 +00:00
Yonggang Luo
1238a65251 nir: Update the comment to call nir_remove_non_entrypoints directly
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23902>
2023-07-03 21:45:35 +00:00
Konstantin Seurer
82aaf1893d nir/builder_opcodes: Do not generate empty intrinsic indices
Gets rid of all the

struct nir_*_indices {
   int _; /* exists to avoid empty initializers */
};

declarations. 14293 loc -> 12900 loc

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23906>
2023-07-03 21:12:45 +00:00
Konstantin Seurer
e379b9ad8c nir/opt_dead_cf: Handle if statements ending in a jump correctly
If a then/else block ends in a jump, the phi nodes do not necessarily
have to reference the always taken branch because they are dead code.
Avoid crashing in this case by only rewriting phis, if the block does
not end in a jump.

cc: mesa-stable

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23150>
2023-07-03 20:36:51 +00:00
Konstantin Seurer
574079e354 nir: Use nir_builder_at
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23883>
2023-07-03 15:21:37 +00:00
Konstantin Seurer
a7cd206937 nir: Add nir_builder_at
Creates and returns a nir_builder from a cursor. The nir_function_impl
is retrieved using said cursor. This should be fine as long as it is not
used on extracted control flow.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23883>
2023-07-03 15:21:37 +00:00
Rhys Perry
3d0e997e99 nir: split nir_lower_mov64
ACO will want to lower the conversions, but preserve the bcsels.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23926>
2023-07-03 10:38:27 +00:00
Yonggang Luo
21a0ca7ce5 nir: Strip the const modifier on nir_function * in nir_foreach_function_with_impl
The function iterator should be able to modified in this foreach loop
And the latter patches needs this

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23960>
2023-07-01 17:39:28 +08:00
Alyssa Rosenzweig
7e42fdac6b nir: Rename nir_reg_{src,dest} -> nir_register_{src,dest}
This frees up the shorter names for the intrinsic-based versions that will
replace them.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23956>
2023-06-30 18:20:48 -04:00
Alyssa Rosenzweig
bed2f3f8e6 nir: Rename load/store_reg -> load/store_register
This frees up the shorter names for the new register-based intrinsics.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23956>
2023-06-30 18:19:51 -04:00
Alyssa Rosenzweig
d1f6bcd1d0 nir: Add b32fcsel_mdg opcode for Midgard
Midgard has both int and float version of b32csel. The backend needs some way to
pick between the two, and it's a lot more convenient to choose in NIR before
going out-of-SSA than in the backend.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23769>
2023-06-30 16:29:35 -04:00
Rhys Perry
25c49e491f aco,ac/llvm,ac/nir,vtn: unify cube opcodes
fossil-db (navi21):
Totals from 17068 (12.79% of 133461) affected shaders:
Instrs: 24743703 -> 24743572 (-0.00%); split: -0.00%, +0.00%
CodeSize: 132579952 -> 132580620 (+0.00%); split: -0.00%, +0.00%
VGPRs: 1227840 -> 1227984 (+0.01%)
Latency: 403180114 -> 403251188 (+0.02%); split: -0.00%, +0.02%
InvThroughput: 75311302 -> 75320892 (+0.01%); split: -0.00%, +0.01%
VClause: 415400 -> 415402 (+0.00%); split: -0.00%, +0.00%
Copies: 1715404 -> 1715258 (-0.01%); split: -0.01%, +0.01%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com> (r600)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23930>
2023-06-30 15:35:03 +00:00
Alyssa Rosenzweig
f0fb8d05e3 nir: Add nir_lower_robust_access pass
Add a pass for bounds checking UBOs, SSBOs, and images to implement robustness.
This pass is based on v3d_nir_lower_robust_access.c, with significant
modifications to be appropriate for common code. Notably:

* v3d-isms are removed.
* Stop generating invalid imageSize() instructions for cube maps, this
  blows up nir_validate with asahi's lowerings.
* Logic to wrap an intrinsic in an if-statement is extracted in anticipation of
  future robustness2 support that will reuse that code path for buffers.
* Misc cleanups to follow modern NIR best practice. This pass is noticeably
  shorter than the original v3d version.

For future support of robustness2, I envision the booleans turning into tristate
enums.

There's a few more knobs added for Asahi's benefit. Apple hardware can do
imageLoad and imageStore to non-buffer images (only).  There is no support for
image atomics. To handle, Asahi implements software lowering for buffer images
and for image atomics. While the hardware is robust, the software paths are not.
So we would like to use this pass to lower robustness for the software paths but
not the hardware paths.

Or maybe we want a filter callback?

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23895>
2023-06-29 22:36:50 +00:00
Christian Gmeiner
36b0cff774 nir/lower_amul: make use nir_shader_clear_pass_flags(..)
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23931>
2023-06-29 19:13:19 +00:00
Christian Gmeiner
fada46cf99 nir: add helper to clear all pass_flags
Will be used in different places so lets move it to a common place.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23931>
2023-06-29 19:13:19 +00:00
Alyssa Rosenzweig
e81b5b972e nir/validate: Assert txf(_ms) matches dimension
We can't txf_ms on non-MS images and we can't txf on MS images. This would have
caught a regression on Asahi.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23892>
2023-06-29 14:17:30 +00:00
Georg Lehmann
44d0b785cc nir/opt_algebraic: combine bitz/bitnz
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
2023-06-29 13:39:30 +00:00
Georg Lehmann
6585209cdd nir/lower_bit_size: mask bitz/bitnz src1 like shifts
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
2023-06-29 13:39:30 +00:00
Georg Lehmann
481a34e82e nir: add single bit test opcodes
These directly map to amd's SALU s_bitcmp0/1.
For VALU we can use v_cmp_class_f32 if the second source is constant.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
2023-06-29 13:39:30 +00:00
Corentin Noël
a8d669b593 nir/split_64bit_vec3_and_vec4: Use the right number of components
Always make sure to correctly deref and store a 64bits variable
from the right number of components.

This fixes the `spec@arb_enhanced_layouts@matching_fp64_types_`
piglit tests for virgl.

Corrects this validation issue:
```
	decl_var  INTERP_MODE_FLAT dvec2[] var_7@2
	decl_var  INTERP_MODE_FLAT dvec2[] var_7@3
...
	vec1 32 ssa_302 = deref_var &var_7@2 (function_temp dvec2[])
	vec1 32 ssa_303 = deref_var &var_7@3 (function_temp dvec2[])
	vec1 32 ssa_304 = deref_array &(*ssa_302)[ssa_301] (function_temp dvec2) /* &var_7@2[ssa_301] */
	vec1 32 ssa_305 = deref_array &(*ssa_303)[ssa_301] (function_temp dvec2) /* &var_7@3[ssa_301] */
	vec1 64 ssa_306 = mov ssa_110.z
	intrinsic store_deref (ssa_305, ssa_306) (wrmask=x, access=0)
error: instr->num_components == glsl_get_vector_elements(dst->type) (../src/compiler/nir/nir_validate.c:632)

	vec4 64 ssa_111 = vec4 ssa_14, ssa_13, ssa_12, ssa_109
	vec1 32 ssa_307 = load_const (0x00000000 = 0.000000)
	vec1 32 ssa_308 = iadd ssa_307, ssa_61
	vec1 32 ssa_309 = deref_var &var_7@2 (function_temp dvec2[])
	vec1 32 ssa_310 = deref_var &var_7@3 (function_temp dvec2[])
	vec1 32 ssa_311 = deref_array &(*ssa_309)[ssa_308] (function_temp dvec2) /* &var_7@2[ssa_308] */
	vec1 32 ssa_312 = deref_array &(*ssa_310)[ssa_308] (function_temp dvec2) /* &var_7@3[ssa_308] */
	vec1 64 ssa_313 = mov ssa_111.w
	intrinsic store_deref (ssa_312, ssa_313) (wrmask=, access=0)
error: (nir_intrinsic_write_mask(instr) & ~component_mask) == 0 (../src/compiler/nir/nir_validate.c:803)
```

Fixes: 496fd59d71 (add pass to split 64 bit vec3/4 variable access)
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23880>
2023-06-29 10:59:57 +00:00
Yonggang Luo
62ce223245 treewide: Switch to use nir_foreach_function_with_impl when possible
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23903>
2023-06-29 08:36:03 +00:00
Yonggang Luo
fde6b51749 nir: Split macro nir_foreach_function_with_impl out of nir_foreach_function_impl
This macro nir_foreach_function_with_impl can be used when func and func->impl are both accessed in
foreach loop

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23903>
2023-06-29 08:36:03 +00:00
Erik Faye-Lund
afa79cd9b8 nir: use imm-helpers
We have to use 1ull instead of 1u because MSVC is stupid...

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
2023-06-29 07:08:19 +00:00
Caio Oliveira
f4c2025e2c nir/print: Print more representations in load_const
In addition to the hexadecimal and float (when applicable), print the
signed and unsigned representations.  Representations may be omitted based
on information about the value:

- If gather types has unambiguous information, we use it;
- Float is omitted for 8 bit values;
- Signed decimal is omitted for positive values;
- Unsigned decimal is omitted for small values (representation is same as hex);

Note for now the "terse form" that appear in SSA uses is unchaged.

Based on a patch by Mike Blumenkrantz.

Examples:

```
// Just used as float. Omitted decimals.
vec4 32 ssa_81 = load_const (0x3f800000, 0x3f800000, 0x3e4ccccd, 0x3f800000) = (1.000000, 1.000000, 0.200000, 1.000000)
vec1 32 ssa_28 = load_const (0x3e4ccccd = 0.200000)

// Just a small integer. Omitted float and decimal.
vec1 32 ssa_45 = load_const (0x00000001)

// Larger positive integers. Omitted float.
vec1 32 ssa_39 = load_const (0x00002000 = 8192)
vec1 32 ssa_30 = load_const (0x000000ff = 255)
vec1 32 ssa_28 = load_const (0x00000010 = 16)

// Integers with negative values.
load_const (0xff = -1 = 255)
load_const (0xff80 = -128 = 65408)
load_const (0xffff = -1 = 65535)

// Same value, in the first case we know is used as an integer.
load_const (0xffffffe0 = -32 = 4294967264)
load_const (0xffffffe0 = -nan = -32 = 4294967264)
```

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
2023-06-28 20:17:18 +00:00
Caio Oliveira
a185736a42 nir/print: Use src_type when printing consts in SSA uses
If the src_type is not available, untie by looking at the results from
nir_gather_ssa_types(). If that is ambiguous, just pick uint.

Now in print_const_from_load() when the type is invalid, print the full
constant form (with both padded hex and float); when the passed type
is valid, print the terse form based on it.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
2023-06-28 20:17:18 +00:00
Caio Oliveira
5d15f4ef28 nir: Extract logic to get dest and srcs types from intrinsic
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
2023-06-28 20:17:18 +00:00
Caio Oliveira
7de530d3df nir: Make a const-friendly way to get the offset_src and arrayed_io_src from intrinsic
The existing helper returns a `nir_src *` so expects a non-const instr.

We plan to use this function in queries that don't modify the shader, so
create (and use internally) a variant that returns the index instead.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
2023-06-28 20:17:18 +00:00
Caio Oliveira
8f64415af7 nir/print: Make NIR_DEBUG=print_consts behavior the default
Now there's a NIR_DEBUG=print_no_inline_consts to omit them.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
2023-06-28 20:17:18 +00:00
Caio Oliveira
260a9167db nir/print: Improve NIR_PRINT=print_consts by using nir_gather_ssa_types()
The two representations are *always* used for `load_const`, but when
inlining the value as SSA source, use just a single terse
representation.

The choice between integer or float is based on the result of
nir_gather_ssa_types(), with a bias for integer when in doubt.

Also remove extra comment `/* */` syntax since the value is already
enclosed by parenthesis.

---

For illustration, here's some instructions from crucible test
func.shader.averageRounded.uint64_t with NIR_DEBUG=print_consts:

BEFORE:

```
vec1 32 con ssa_23 = load_const (0xfffffffc = -nan)
vec1 32 div ssa_24 = iand ssa_13, ssa_23 /*(0xfffffffc = -nan)*/
vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000)
vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1 /*(0x00000002 = 0.000000)*/, ssa_25 /*(0x00000024 = 0.000000)*/) (access=0, align_mul=1073741824, align_offset=36, range_base=0, range=-1)
vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000)
vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000)
vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 /*(0x00000002 = 0.000000)*/
vec1 32 con ssa_30 = ishl ssa_29, ssa_28 /*(0x00000007 = 0.000000)*/
vec1 32 con ssa_31 = load_const (0x7b000808 = 664776890994587263929995856502063104.000000)
vec1 32 con ssa_32 = ior ssa_31 /*(0x7b000808 = 664776890994587263929995856502063104.000000)*/, ssa_30
```

AFTER:

```
vec1 32 con ssa_23 = load_const (0xfffffffc = -nan)
vec1 32 div ssa_24 = iand ssa_13, ssa_23 (0xfffffffc)
vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000)
vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1 (0x2), ssa_25 (0x24)) (access=0, align_mul=1073741824, align_offset=36, range_base=0, range=-1)
vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000)
vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000)
vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 (0x2)
vec1 32 con ssa_30 = ishl ssa_29, ssa_28 (0x7)
vec1 32 con ssa_31 = load_const (0x7b000808 = 664776890994587263929995856502063104.000000)
vec1 32 con ssa_32 = ior ssa_31 (0x7b000808), ssa_30
```

and some instructions from crucible test func.gs.basic with NIR_DEBUG=print_consts,
now showing float representation being selected:

BEFORE:

```
vec4 32 ssa_10 = load_const (0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)
vec4 32 ssa_9 = intrinsic load_deref (ssa_42) (access=0)
vec4 32 ssa_11 = fadd ssa_9, ssa_10 /*(0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)*/
```

AFTER:

```
vec4 32 ssa_10 = load_const (0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)
vec4 32 ssa_9 = intrinsic load_deref (ssa_42) (access=0)
vec4 32 ssa_11 = fadd ssa_9, ssa_10 (0.200000, 0.200000, 0.000000, 0.000000)
```

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
2023-06-28 20:17:18 +00:00
Caio Oliveira
3cfdab8f92 nir: Allow nir_gather_ssa_types() to ignore regs instead of assert
If we infer a type for a reg, just ignore and keep going.  This will allow
to use this pass even when registers are present.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
2023-06-28 20:17:18 +00:00
Alyssa Rosenzweig
190b1fdc64 nir: Convert to nir_foreach_function_impl
Done by hand at each call site but going very quickly with funny Vim motions and
common regexes. This is a very common idiom in NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23807>
2023-06-27 22:44:04 +00:00
Alyssa Rosenzweig
19daa9283c nir: Add nir_foreach_function_impl helper
Most users of nir_foreach_function actually want the nir_function_impl, not the
nir_function, and want to skip empty functions (though some graphics-specific
passes sometimes fail to do that part). Add a nir_foreach_function_impl macro
to make that case more ergonomic.

   nir_foreach_function_impl(impl, shader) {
      ...
      foo(impl)
   }

is equivalent to:

   nir_foreach_function(func, shader) {
      if (func->impl) {
         ...
         foo(func->impl);
      }
   }

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23807>
2023-06-27 22:44:04 +00:00
Rhys Perry
8649bde78f nir/opt_intrinsic: optimize quad vote
Optimizes a quadAll()/quadAny() pattern created by dxil-spirv:
7adc87d4de

dxil-spirv can't use clustered reductions because they are not guaranteed
to include helper invocations.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
2023-06-27 18:53:50 +00:00
Rhys Perry
58f8e0e2a0 nir,aco: add INCLUDE_HELPERS index to reduce intrinsic
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
2023-06-27 18:53:50 +00:00
Rhys Perry
48674a1799 nir/peephole_select: allow some invocation broadcast intrinsics
fossil-db (navi21):
Totals from 3 (0.00% of 133428) affected shaders:
Instrs: 2074 -> 2083 (+0.43%)
CodeSize: 10596 -> 10692 (+0.91%)
Latency: 75754 -> 75946 (+0.25%)
InvThroughput: 16900 -> 16975 (+0.44%)
Copies: 312 -> 309 (-0.96%)
Branches: 150 -> 132 (-12.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
2023-06-27 18:53:49 +00:00
Alyssa Rosenzweig
069cca9d66 treewide: Remove unused builders
-Wunused-variables kicks in now that it can see through the init.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
2023-06-27 18:13:02 +00:00
Alyssa Rosenzweig
173b9ee69a treewide: Use nir_builder_create more
perl -p0e 's/nir_builder_init\(&([^,]*), /\1 = nir_builder_create(/g' -i $(git grep -l nir_builder_init)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
2023-06-27 18:13:02 +00:00
Alyssa Rosenzweig
815efcdf7e nir: Use nir_builder_create
perl -p0e 's/nir_builder ([^;]*);\s*nir_builder_init\(&\1, /nir_builder \1 = nir_builder_create(/g' -i $(git grep -l nir_builder_init)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
2023-06-27 18:13:02 +00:00