Commit graph

72014 commits

Author SHA1 Message Date
Adam Jackson
bafdafa7b2 glx: Fix missing bit decl for EXT_texture_integer
Missing from:

    commit b15aba940a
    Author: Adam Jackson <ajax@redhat.com>
    Date:   Tue Jul 21 11:43:42 2015 -0400

	glx: Fix image size computation for EXT_texture_integer (v2)

Signed-off-by: Adam Jackson <ajax@redhat.com>
2015-07-31 13:37:19 -04:00
Matt Turner
616355160d glsl: Initialize parse-state in constructor of lower_subroutine.
Static analysis tools don't like partial object initializations.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2015-07-31 10:33:03 -07:00
Adam Jackson
b15aba940a glx: Fix image size computation for EXT_texture_integer (v2)
Without this this extension basically can't work in indirect contexts,
TexImage2D will compute the image size as 0 and we'll send no image data
to the server.

v2: Add EXT_texture_integer to the client extension list too (Ian)

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2015-07-31 12:32:16 -04:00
Marek Olšák
3050978864 radeonsi: copy *8_SNORM bits exactly in resource_copy_region
Disabling the FP16 mode didn't help.

If needed, we can use this trick for blits too, but not for scaled blits.

+ 4 piglits

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-07-31 16:49:17 +02:00
Marek Olšák
64d3130994 r600g: early exit in r600_clear if there's nothing to do
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-07-31 16:49:17 +02:00
Marek Olšák
f9c4953f99 radeonsi: early exit in si_clear if there's nothing to do
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-07-31 16:49:17 +02:00
Marek Olšák
190a40580f radeonsi: fix a regression since the resource_copy_region cleanup
Broken since:
    46b2b3b - radeonsi: don't change pipe_resource in resource_copy_region

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91444

Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2015-07-31 16:49:17 +02:00
Marek Olšák
3ca2132058 radeonsi: fix broken st/nine from merging tessellation
st/nine uses GENERIC slots greater than 60.
2015-07-31 16:49:17 +02:00
Marek Olšák
2d3ae154ba radeonsi: move CP DMA functions to their own file
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-07-31 16:49:17 +02:00
Marek Olšák
3063c5e3d3 radeonsi: add a debug flag that disables printing ISA in shader dumps 2015-07-31 16:49:17 +02:00
Marek Olšák
2dcbd427da radeonsi: add a debug flag that disables printing TGSI in shader dumps
Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-07-31 16:49:17 +02:00
Marek Olšák
ac19a896d3 radeonsi: add a debug flag that disables printing the LLVM IR in shader dumps
This is for shader-db and should reduce size of shader dumps.
2015-07-31 16:49:17 +02:00
Marek Olšák
7dd1f45bc4 radeonsi: store shader disassemblies in memory for future users
This will be used by the new ddebug pipe. I'm including it now to avoid
conflicts with other patches.
2015-07-31 16:49:16 +02:00
Marek Olšák
1bbe408363 radeonsi: don't use llvm.AMDIL.fraction for FRC and DFRAC
There are 2 reasons for this:
- LLVM optimization passes can work with floor
- there are patterns to select v_fract from floor anyway

There is no change in the generated code.
2015-07-31 16:49:16 +02:00
Marek Olšák
8559f6ce62 gallium/radeon: re-enable unsafe math for graphics shaders
This reverts commit 4db985a5fa.

The grass no longer disappears, which was the reason the commit was reverted.
This might affect tessellation. We'll see.

Totals from affected shaders:
SGPRS: 151672 -> 150232 (-0.95 %)
VGPRS: 90620 -> 89776 (-0.93 %)
Code Size: 3980472 -> 3920836 (-1.50 %) bytes
LDS: 67 -> 67 (0.00 %) blocks
Scratch: 1357824 -> 1202176 (-11.46 %) bytes per wave

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2015-07-31 16:49:16 +02:00
Marek Olšák
12a197b2d5 gallium/radeon: don't use rsq_action
Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-07-31 16:49:16 +02:00
Marek Olšák
681dbcf690 gallium/radeon: move r600-specific code to r600g
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2015-07-31 16:49:16 +02:00
Marek Olšák
9a4c57afe4 gallium/radeon: remove unused variables and old comments
Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-07-31 16:49:16 +02:00
Marek Olšák
b9dad585e6 gallium/radeon: remove build_intrinsic and build_tgsi_intrinsic
duplicated now

Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-07-31 16:49:16 +02:00
Marek Olšák
0c805b6240 gallivm: add LLVMAttribute parameter to lp_build_intrinsic
This will help remove some duplicated code from radeon.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-07-31 16:49:16 +02:00
Marek Olšák
488a83637f gallium/util: clear up that debug_get_flags_option returns a 64-bit mask
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
2015-07-31 16:49:16 +02:00
Marek Olšák
b0528118df radeonsi: completely rework updating descriptors without CP DMA
The patch has a better explanation. Just a summary here:
- The CPU always uploads a whole descriptor array to previously-unused memory.
- CP DMA isn't used.
- No caches need to be flushed.
- All descriptors are always up-to-date in memory even after a hang, because
  CP DMA doesn't serve as a middle man to update them.

This should bring:
- better hang recovery (descriptors are always up-to-date)
- better GPU performance (no KCACHE and TC flushes)
- worse CPU performance for partial updates (only whole arrays are uploaded)
- less used IB space (no CP_DMA and WRITE_DATA packets)
- simpler code
- hopefully, some of the corruption issues with SI cards will go away.
  If not, we'll know the issue is not here.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-07-31 16:49:16 +02:00
Francisco Jerez
781dc7c0e1 i965/fs: Fix regression with SIMD8 VS since b5f1a48e23.
With num_direct_uniforms == 0 there's no space allocated in the
param_size array for the one block of direct uniforms -- On the FS
stage this would be a harmless no-op because it would simply re-set
one of the param_size entries allocated for the sampler units to zero,
but on the VS stage it has been reported to cause memory corruption
followed by a crash -- Surprising how a full piglit run on Gen8 didn't
catch it.

Reported-and-reviewed-by: "Lofstedt, Marta" <marta.lofstedt@intel.com>
2015-07-31 16:20:52 +03:00
Ben Widawsky
383558c564 i965/gen9: Add hs, ds, and cs thread + urb info
For SKL: These are the production values.

For BXT: These are low estimates to enable platforms.

This patch was originally part of
i965/skl: Add production thread counts and URB size
but was split out at Jordan's request (which I found to be reasonable).

Note on stable inclusion: 10.6 does not care about hs, and ds. It does care
about cs, but since Jordan was the one that asked me to extract it, I'll leave
it up to him to deal with a backport to stable is required.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-07-30 22:39:11 -07:00
Ben Widawsky
3cb5801003 i965/bxt: Use more conservative thread counts
Since we really do not know what may occur in the future, pick a more
conservative value for thread counts until we know better what values are
correct. As far as I can tell, the old values will work fine, but some of the
registers seem to indicate that going even lower is possible and the purpose of
having early support is to enable as many configurations that can possibly
exist (we can trim things down after platforms begin shipping later).

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-07-30 22:39:11 -07:00
Ben Widawsky
7eaacc1678 i965/skl: Add production thread counts and URB size
This patch adjusts the SKL values to the best known values we have.

v2: Remove HS/DS/CS fields. Adding this makes most sense to add to the
GEN9_FEATURES macro, however, doing that would require updating BXT values, and
Jordan requested I not do that. Conveniently, this request makes a lot of sense
wrt to stable backport as HS, and DS do not even exist there.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-07-30 22:39:11 -07:00
Eric Anholt
7830e465a5 vc4: Lower uniform loads to scalar in NIR.
This also moves the vec4-to-byte-addressing math into NIR, so that
algebraic has a chance at it.
2015-07-30 15:47:12 -07:00
Eric Anholt
5a8c57b522 vc4: Move some FS input lowering into NIR. 2015-07-30 15:47:12 -07:00
Eric Anholt
13ddd48b97 vc4: Move program keys to the header file.
I want to be able to inspect them from other files for lowering passes in
NIR.
2015-07-30 15:47:12 -07:00
Eric Anholt
27f728cdc5 vc4: Lower NIR inputs to scalar as well.
For now this is just scalarizing, but it also means we'll get to dump a
bunch of QIR-based lowering in a moment.
2015-07-30 15:47:12 -07:00
Eric Anholt
b85f6ae4b2 vc4: Start adding a NIR-based output lowering pass.
For now, this just splits up store_output intrinsics to be scalars, and
drops unused outputs in the coordinate shader.  My goal is to be able to
drop a bunch of my VC4-specific optimization by letting NIR handle it.
2015-07-30 15:47:11 -07:00
Eric Anholt
c93ffd661a vc4: Mark our shaders as single-threaded.
I had my understanding of this bit flipped.  We're using the full register
space, so we need to say so.
2015-07-30 15:46:28 -07:00
Eric Anholt
df3005de18 vc4: Avoid leaking indirect array access UBOs. 2015-07-30 15:46:28 -07:00
Eric Anholt
86541cf8ce vc4: Avoid overflowing various static tables. 2015-07-30 15:46:27 -07:00
Eric Anholt
d0173bce37 vc4: Fix return values from recent validation changes. 2015-07-30 15:46:27 -07:00
Kai Wasserbäch
a5b3b24958 docs: trivial cleanup of GL3.txt, remove redundant radeonsi entries.
Follow-up to 1b2b0e42ce

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-31 07:28:17 +10:00
Dave Airlie
518abd0bbe st/mesa: don't draw instead of asserting in transform feedback
if we get a request to take the count from feedback, but there
is no buffer to take it from, just draw as if we got 0 vertices
so nothing.

This fixes this assert killing the ogl conform, and a piglit
test I've sent.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-31 07:27:29 +10:00
Timothy Arceri
fdb8487613 mesa: remove now unused _mesa_get_uniform_location
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-07-30 22:00:56 +10:00
Timothy Arceri
7f5f7d15fb mesa: remove now unused subscript validations
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-07-30 22:00:50 +10:00
Timothy Arceri
8cd2f88845 mesa: fix and simplify resource query for arrays
This removes the need for multiple functions designed to validate an array
subscript and replaces them with a call to a single function.

The change also means that validation is now only done once and the index
is retrived at the same time, as a result the getUniformLocation code can
be simplified saving an extra hash table lookup (and yet another
validation call).

This chage also fixes some tests in:
ES31-CTS.program_interface_query.uniform

V3: rebase on subroutines, and move the resource index array == 0
check into _mesa_GetProgramResourceIndex() to simplify things further

V2: Fix bounds checks for program input/output, split unrelated comment fix
and _mesa_get_uniform_location() removal into their own patch.

Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-07-30 22:00:45 +10:00
Neil Roberts
3a21e4bd26 i965/bxt: Don't use brw_device_info_skl_early on BXT
Previously it could end up using the “SKL early” device on BXT
depending on the revision number. This would probably break things
because for example has_llc would be wrong.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-30 11:45:27 +01:00
Timothy Arceri
75a96cedf7 glsl: set stage flag for structs and arrays in resource list
This fixes the remaining failing tests in:
ES31-CTS.program_interface_query.uniform-types

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-07-30 19:33:33 +10:00
Dave Airlie
1b2b0e42ce docs: consolidate radeonsi in GL3.txt
move into DONE for GL4.0 and GL4.1

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-30 09:00:42 +01:00
Dave Airlie
af1e6aa75b radeonsi: enable GL4.1 and update documentation (v2)
This enables GL4.1 for radeonsi, and updates the
docs in the correct places.

v2: enable only for llvm 3.7 which has fixes in place.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-30 09:00:25 +01:00
Dave Airlie
3c73c41871 radeonsi: add GS multiple streams support (v2)
This is the final piece for ARB_gpu_shader5,

The code is based on the r600 code from Glenn Kennard,
and myself.

While developing this, I'm not 100% sure of all the calculations
made in the GS registers, this is why the max_stream is worked
out there and used to limit the changes in registers. Otherwise
my initial attempts either regressed GS texelFetch tests
or primitive-id-restart. The current code has no regressions
in piglit.

This commit doesn't enable ARB_gpu_shader5, since that just
bumps the glsl level to 4.00, so I'll just do a separate patch
for 4.10.

v1.1: fix bug introduced in rebase.
v2: Address Marek's review comments,
remove my llvm stream code for simpler C,
move gsvs_ring and gs_next_vertex to arrays.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-07-30 09:00:17 +01:00
Anuj Phogat
c73a13e953 Delete unused functions in format parser
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-07-29 14:46:32 -07:00
Anuj Phogat
92994742d0 i965: Change the type of max_{vs, hs, ...}_threads variables to unsigned
Fixes following compiler warning:
brw_cs.cpp:386:27: warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-07-29 14:46:31 -07:00
Anuj Phogat
2484263fe9 Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-07-29 14:46:30 -07:00
Jose Fonseca
8413822c8c gallium/auxiliary: Ensure c99_math.h is included.
As it is needed for exp2.

Trivial.
2015-07-29 21:25:10 +01:00
Roland Scheidegger
2b916c6e47 c99_math: (trivial) implement exp2 for MSVC too
Unsurprisingly doesn't build otherwise with old msvc.
2015-07-29 22:20:04 +02:00