Commit graph

72014 commits

Author SHA1 Message Date
Frank Binns
2900e8ca90 egl/x11: fix use of EGL_BAD_NATIVE_WINDOW
Commit 4ed23fd590 introduced some calls to _eglError inappropriately
passing it EGL_BAD_NATIVE_WINDOW. This was actually harmless in two of the
cases as _eglError gets called later on with a more appropriate error code
but (just to be safe) switch these to _eglLog calls instead.

The final case is a little trickier as it actually needs to set an error
of which the following are available (according to the EGL spec):
EGL_BAD_MATCH, EGL_BAD_CONFIG, EGL_BAD_NATIVE_(PIXMAP|WINDOW) and
EGL_BAD_ALLOC.

Of these, EGL_BAD_ALLOC seems to be the most appropriate given that
failure can occur either as a result of xcb_get_setup failing due to an
earlier error on the connection (where the most commonly occurring error
code is XCB_CONN_CLOSED_MEM_INSUFFICIENT) or as a result of the
xcb_screen_iterator_t 'rem' field being 0.

In addition to this, commit af2aea40d2 unconditionally set the error to
EGL_BAD_NATIVE_WINDOW when creating a window or pixmap surface with a NULL
native handle. Change this to correctly set the error based on surface
type.

v2: Updated patch description (Emil Velikov)
    Return EGL_BAD_NATIVE_PIXMAP when eglCreatePixmapSurface is called
    with a NULL native pixmap handle

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-08-13 17:36:06 +01:00
Timothy Arceri
8dffa89e01 mesa: remove extern from texture function
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-08-13 21:57:30 +10:00
Timothy Arceri
b8f63b3c10 glsl: make linker error message more informative
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-08-13 21:57:20 +10:00
Topi Pohjolainen
1bba29ed40 i965: Stop aux data compare preventing program binary re-use
Items in the program cache consist of three things: key, the data
representing the instructions and auxiliary data representing
uniform storage. The data consisting of instructions is stored into
a drm buffer object while the key and the auxiliary data reside in
malloced section. Now the cache uploading is equipped with a check
that iterates over existing items and seeks to find a another item
using identical instruction data than the one being just uploaded.
If such is found there is no need to add another section into the
drm buffer object holding identical copy of the existing one. The
item just being uploaded should instead simply point to the same
offset in the underlying drm buffer object.

Unfortunately the check for the matching instruction data is
coupled with a check for matching auxiliary data also. This
effectively prevents the cache from ever containing two items
that could share a section in the drm buffer object.

The constraint for the instruction data and auxiliary data to
match is, fortunately, unnecessary strong. When items are stored
into the cache they will anyway contain their own copy of the
auxiliary data (even if they matched - which they in real world
never will). The only thing the items would be sharing is the
instruction data and hence we should only check for that to match
and nothing else.

No piglit regression in jenkins.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-08-13 13:37:49 +03:00
Topi Pohjolainen
12a66d91f6 i965: Only write program to cache when it doesn't exist yet
Current logic re-writes the same data when existing data is found.
Not that this actually matters at the moment in practice, the
contraint for finding matching data is too severe to ever allow
data to be shared between two items in the cache.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-08-13 13:37:49 +03:00
Topi Pohjolainen
b4897eb70a i965: Rename brw_upload_item_data to brw_alloc_item_data
and simplify the interface to take directly the size and to return
the offset. The routine does nothing more than allocate, it doesn't
upload anything.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-08-13 13:37:49 +03:00
Tapani Pälli
853853b2ac mesa: update MaxShaderStorageBlockSize to 2^27
Extension spec originally required 2^24 but 2^27 is the minimum value
required by OpenGL 4.5 and OpenGL ES 3.1 specifications.

Fixes:
   ES31-CTS.shader_storage_buffer_object.basic-max

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-08-13 12:55:29 +03:00
Tapani Pälli
24695f4b27 mesa: fix name returned for XFB varyings
_mesa_get_program_resource_name has logic to append '[0]' in name
if variable is an array, this should be skipped for XFB varyings
that have array index already appended.

v2: fix comment, change also GL_NAME_LENGTH query to match
    the behaviour

Fixes:
   ES31-CTS.program_interface_query.transform-feedback-types

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
2015-08-13 12:55:17 +03:00
Edward O'Callaghan
86a72ee48e mesa: Fix printf format specifier warn of the ptrdiff_t
See §7.19.6.1, paragraph 7 of the ISO C specification.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-08-13 01:25:26 +02:00
Marek Olšák
8c0b943e87 r600g: allow setting geometry shader sampler states
We were ignoring them. This is both hilarious and sad.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-13 01:25:26 +02:00
Marek Olšák
d335aad11b r600g: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.

Should fix piglit: gl-1.4-polygon-offset (formerly a glean test)
(untested, ported from radeonsi)

Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-08-13 01:25:26 +02:00
Marek Olšák
bfac8ba9d3 radeonsi: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.

Fixes piglit: gl-1.4-polygon-offset (formerly a glean test)

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-08-13 01:25:26 +02:00
Marek Olšák
8ae88105b6 radeonsi: enable VS_OUT_MISC_SIDE_BUS_ENA
This is recommended for better performance.
Diag tests always enable this.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-13 01:25:26 +02:00
Marek Olšák
e7a52a5cb8 radeonsi: add support for gl_PrimitiveID in the fragment shader
It must be obtained from the VS.

The GS scenario A must be enabled for PrimID to be generated for the VS.

+ 4 piglits

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-13 01:25:26 +02:00
Marek Olšák
8e11be0ddb radeonsi: move VGT_GS_MODE to the VS state
The VS will want to select GS scenario A here (VS with PrimitiveID).

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-13 01:25:26 +02:00
Rob Clark
bdc564b942 freedreno/a4xx: format updates
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-12 18:37:43 -04:00
Rob Clark
500025a237 freedreno/a3xx+a4xx: add texture buffer object support
Basic texture buffer support.  Should be straightforward to add first/
last_element support.  And with a bit of work in ir3 emulate larger
texture buffer sizes.  But this seems to be enough for stk gl31 render
paths.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-12 18:37:43 -04:00
Rob Clark
fb07c49f48 ttn: add buffer texture type
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-12 18:37:43 -04:00
Rob Clark
aab3912f21 freedreno/ir3: 'keeps' need neighbors found too
This shows up with a glamor shader, which does a TXF and uses the result
for conditional kill.  Before we wouldn't group the fanin (collect)
neighbors which need to be allocated adjacently at RA, resulting in
badness.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-12 18:37:43 -04:00
Rob Clark
6e04020dd7 freedreno/ir3/print: print left/right neighbors too
When debugging compiler, this is useful to see.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-12 18:37:43 -04:00
Rob Clark
0667962103 freedreno/ir3: use nir pass to lower const to scalar
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-12 18:37:43 -04:00
Rob Clark
8885f2befa freedreno/a4xx: point-size and spritelist fixes
a4xx needs similar treatment as 995f55a6

Also fixup a few point-size and vpsrepl issues and drop fix_blit_fp()
hack previously needed for mem2gmem.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-12 18:37:43 -04:00
Rob Clark
f72fead4a2 freedreno: cap cleanups
Move a few things around to group stuff that is common to a3xx/a4xx
together.  Also, introduce is_ir3() for things that are more specific to
the compiler / shader-ISA than to the gpu generation.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-12 18:37:43 -04:00
Rob Clark
81d2fd91a9 mesa: add NV_read_{depth,stencil,depth_stencil} extensions
These extensions allow reading depth/stencil for GLES contexts, which is
useful for tools like apitrace.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-08-12 18:37:43 -04:00
Jason Ekstrand
078aef0e97 i965/shader: Don't use OptimizeForAOS for NIR vec4 vertex shaders
Shader-db results for vec4 programs using NIR on HSW:

   total instructions in shared programs: 1838157 -> 1828469 (-0.53%)
   instructions in affected programs:     275978 -> 266290 (-3.51%)
   helped:                                2827
   HURT:                                  244
   GAINED:                                0
   LOST:                                  0

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2015-08-12 14:12:47 -07:00
Nanley Chery
91698d1206 mesa/teximage: report the correct function which triggered the error
This function would always report that a dimension or size error occurred
in glTexImage even when it was called from glCompressedTexImage. Replace
the static string with the dynamically determined caller name.

Reviewed-by: Tapani Palli <tapani.palli@intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2015-08-12 13:48:45 -07:00
Oded Gabbay
5f1d5b1c78 mesa/formats: don't byteswap when building array formats
Because we build here an array format, we don't need to swap the
bytes for big endian.
If it isn't an array format, the bytes will be swapped in
_mesa_format_convert.

v2: remove temp variable

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
2015-08-12 08:28:31 -07:00
Jason Ekstrand
e3eb91af80 mesa/formats: Don't flip channels of null array formats
Before, if we encountered an array format of 0 on a BE system, we would
flip all the channels even though it's an invalid format.  This would
result in a mostly invalid format with a swizzle of yyyy or wwww.  Instead,
we should just return 0 if the array format stashed in the format info is
invalid.

Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
2015-08-12 08:28:31 -07:00
Jason Ekstrand
28d1a506c8 mesa/formats: Fix swizzle flipping for big-endian targets
The swizzle defines where in the format you should look for any given
channel.  When we flip the format around for BE targets, we need to change
the destinations of the swizzles, not the sources.  For example, say the
format is an RGBX format with a swizzle of xyz1 on LE.  Then it should be
wzy1 on BE;  however, the code as it was before, would have made it 1zyx on
BE which is clearly wrong.

Reviewed-by: Iago Toral <itoral@igalia.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
2015-08-12 08:28:31 -07:00
Jason Ekstrand
3941539179 mesa/formats: Only do byteswapping for packed formats
Reviewed-by: Iago Toral <itoral@igalia.com>
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
2015-08-12 08:28:31 -07:00
Matt Turner
02a4fe22b1 configure.ac: Always define __STDC_LIMIT_MACROS.
... which ensures that we get defines like LONG_MAX in C++.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-08-11 15:21:03 -07:00
Matt Turner
2265321834 i965: Optimize brw_inst_set_bits() and brw_compact_inst_set_bits().
Cuts about 2k of .text.

   text     data      bss      dec      hex  filename
5017141   197160    27672  5241973   4ffc75  i965_dri.so before
5014981   197160    27672  5239813   4ff405  i965_dri.so after

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-11 15:13:17 -07:00
Matt Turner
9fa70fef22 i965: Optimize brw_inst_bits() and brw_compact_inst_bits().
Cuts about 1k of .text.

   text     data      bss      dec      hex  filename
5018165   197160    27672  5242997   500075  i965_dri.so before
5017141   197160    27672  5241973   4ffc75  i965_dri.so after

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-11 15:13:10 -07:00
Emil Velikov
1e53df7064 docs: add news item and link release notes for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-08-11 19:00:56 +01:00
Emil Velikov
d32c45ca7b docs: add sha256 checksums for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 99793e2541)
2015-08-11 19:00:55 +01:00
Emil Velikov
c4b4bad68a docs: add release notes for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 6b2fcee64e)
2015-08-11 19:00:55 +01:00
Marek Olšák
b88f14702d gallium/radeon: fix r600g build if LLVM is disabled
MESA_LLVM_VERSION_PATCH is undefined.

Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Tested-by: Benjamin Bellec <b.bellec@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-11 14:46:54 +02:00
Grazvydas Ignotas
5054588211 r600g: use a bitfield to track dirty atoms
r600 currently has 73 atoms and looping through their dirty flags has
become costly because checking each flag requires a pointer
dereference before the read. To avoid having to do that add additional
bitfield which can be checked really quickly thanks to tzcnt instruction.

id field was added to struct r600_atom but that doesn't affect memory
usage for both 32 and 64 bit CPUs because it was stuffed into padding.

The performance improvement is ~2% for benchmarks that can have FPS in
the thousands but is hardly measurable in "real" programs.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-08-11 14:46:54 +02:00
Grazvydas Ignotas
c58534c138 r600g: don't mark unused atom dirty
On evergreen config_state is not used, so don't mark it dirty.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-08-11 14:46:54 +02:00
Grazvydas Ignotas
85adde30a4 r600g: use a helper to add an initialized atom
Instead of writing to rctx->atoms directly use a helper to take
advantage of assert checks.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-08-11 14:46:54 +02:00
Grazvydas Ignotas
3206d4ed44 gallium/radeon: use helper functions to mark atoms dirty
This is analogous to r300_mark_atom_dirty() used by r300, and will
be used by later patches. For common radeon code, appropriate helper
is called through a function pointer.

No functional changes.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-08-11 14:46:53 +02:00
Francisco Jerez
3c04a90e91 docs: Mark ARB_shader_image_load_store as done on i965. 2015-08-11 15:07:40 +03:00
Francisco Jerez
d03c65793a i965: Expose ARB_shader_image_load_store.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-11 15:07:40 +03:00
Francisco Jerez
13a04abc27 i965/fs: Clamp image array indices to the array bounds on IVB.
This fixes the spec@arb_shader_image_load_store@invalid index bounds
piglit tests on IVB, which were causing a GPU hang and then a crash
due to the invalid binding table index result of the array index
calculation.  Other generations seem to behave sensibly when an
invalid surface is provided so it doesn't look like we need to care.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-08-11 15:07:40 +03:00
Francisco Jerez
a47ae8de2c i965/fs: Translate image load, store and atomic NIR intrinsics.
v2: Move array coordinate workaround into the surface builder.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-11 15:07:40 +03:00
Francisco Jerez
912ef52c29 i965/fs: Handle image uniforms in NIR programs.
v2: Move the image_params array back to brw_stage_prog_data.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-11 15:07:40 +03:00
Francisco Jerez
4af27145fe i965: Implement logic to set up and upload an image uniform.
v2: Move the image_params array back to brw_stage_prog_data.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-08-11 15:07:40 +03:00
Francisco Jerez
84431c1f1d i965: Teach type_size() about the size of an image uniform.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-08-11 15:07:40 +03:00
Francisco Jerez
caae52561d i965/fs: Implement image load, store and atomic.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Move array coordinate workaround into the surface builder.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-11 15:07:39 +03:00
Francisco Jerez
7e8be00010 i965/fs: Import image format conversion primitives.
Define bitfield packing, unpacking and type conversion operations in
terms of which the image format conversion code will be implemented.
These don't directly know about image formats: The packing and
unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit
widths as arguments, determining the bitfield position of each
component.  Most of the remaining functions perform integer, fixed
point normalized, and floating point type conversions, mapping between
a target type with per-component bit widths given by a parameter and a
matching native representation of the same type.

v2: Drop VEC4 suport.
v3: Rebase.
v4: Fix clamping of negative floats in the unsigned case of
    emit_convert_to_scaled().

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-11 15:07:39 +03:00