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Author SHA1 Message Date
Dave Airlie
7b6cd912a5 mesa/st: get rid of ST_CALLOC_STRUCT use CALLOC_STRUCT 
Just tie in the CALLOC_STRUCT/FREE mechanism.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14325>
 2022-01-18 22:20:18 +00:00
Dave Airlie
05c8fb6335 mesa/st/perfmon: rebalance CALLOC_STRUCT/FREE 
this was using FREE but ST_CALLOC_STRUCT, so fix the other way.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14325>
 2022-01-18 22:20:18 +00:00
Dave Airlie
7c79c9bfb1 mesa: rebalance the CALLOC_STRUCT/FREE force. 
There were some CALLOC_STRUCT that were using free, rebalance this.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14325>
 2022-01-18 22:20:18 +00:00
Dave Airlie
3b26dbf8f1 mesa/program: don't use CALLOC_STRUCT for instructions. 
Figuring out the frees here was too much for me.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14325>
 2022-01-18 22:20:18 +00:00
Cristian Ciocaltea
279cc37ac0 freedreno/ci: Fix dEQP tests expectations on A530 
Add a new entry to the 'fails' list.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14413>
 2022-01-18 18:42:05 +00:00
Cristian Ciocaltea
da709e8aa7 panfrost/ci: Fix piglit tests expectations on G52 
Remove the successful tests from the 'fails' list.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14413>
 2022-01-18 18:42:05 +00:00
Cristian Ciocaltea
214ea8e018 iris/ci: Fix piglit tests expectations on amly 
Found two tests that started to show a flaky behavior, although they are
not detected as such by the test runner. Depending on their presence in
the 'fails' list, they are reported as "UnexpectedPass" or "Fail".

Let's fix this by moving them to the 'flaky' list.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14413>
 2022-01-18 18:42:05 +00:00
Cristian Ciocaltea
05c6dea68b iris/ci: Fix whl dEQP expectations 
Remove the successful tests from the 'fails' list.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14413>
 2022-01-18 18:42:05 +00:00
Charles Baker
dcb2f48ed6 zink: Enable VK_KHR_image_format_list for VK_KHR_imageless_framebuffer 
Validation layer reports that VK_KHR_imageless_framebuffer depends on
VK_KHR_image_format_list and that the latter must be enabled explicitly
with the former.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14570>
 2022-01-18 18:30:22 +00:00
Mike Blumenkrantz
97da9e4bf4 Revert "zink: update gfx_pipeline_state.vertex_strides when necessary" 
This reverts commit a21d2bfd77.

my brain was still on vacation and this doesn't do anything

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14593>
 2022-01-18 18:18:56 +00:00
Connor Abbott
9c9e8c3349 nir: Reorder ffma and fsub combining 
It's relatively common to do something like "a * b - c", which on most
GPUs can be implemented in a single instruction. Before
opt_algebraic_late this will be something like
"fadd(fmul(a, b), fneg(c))", and we want to turn it info
"ffma(a, b, fneg(c))". But because the fsub pattern was first we
instead turned it into "fsub(fmul(a, b), c)". Fix this by reordering
them.

Selected shader-db results on freedreno:

total instructions in shared programs: 1561330 -> 1551619 (-0.62%)
instructions in affected programs: 780272 -> 770561 (-1.24%)
helped: 1941
HURT: 491
helped stats (abs) min: 1 max: 147 x̄: 7.98 x̃: 4
helped stats (rel) min: 0.07% max: 30.77% x̄: 4.36% x̃: 3.17%
HURT stats (abs)   min: 1 max: 307 x̄: 11.76 x̃: 5
HURT stats (rel)   min: 0.09% max: 18.71% x̄: 2.26% x̃: 1.38%
95% mean confidence interval for instructions value: -4.57 -3.41
95% mean confidence interval for instructions %-change: -3.21% -2.84%
Instructions are helped.

total nops in shared programs: 358926 -> 356263 (-0.74%)
nops in affected programs: 167116 -> 164453 (-1.59%)
helped: 1395
HURT: 859
helped stats (abs) min: 1 max: 108 x̄: 6.80 x̃: 3
helped stats (rel) min: 0.17% max: 100.00% x̄: 19.15% x̃: 10.57%
HURT stats (abs)   min: 1 max: 307 x̄: 7.95 x̃: 3
HURT stats (rel)   min: 0.00% max: 381.82% x̄: 20.04% x̃: 10.00%
95% mean confidence interval for nops value: -1.77 -0.59
95% mean confidence interval for nops %-change: -5.55% -2.87%
Nops are helped.

total non-nops in shared programs: 1202404 -> 1195356 (-0.59%)
non-nops in affected programs: 496682 -> 489634 (-1.42%)
helped: 1951
HURT: 265
helped stats (abs) min: 1 max: 39 x̄: 4.02 x̃: 3
helped stats (rel) min: 0.07% max: 15.38% x̄: 2.97% x̃: 1.96%
HURT stats (abs)   min: 1 max: 22 x̄: 2.97 x̃: 2
HURT stats (rel)   min: 0.05% max: 10.00% x̄: 1.14% x̃: 0.75%
95% mean confidence interval for non-nops value: -3.38 -2.99
95% mean confidence interval for non-nops %-change: -2.60% -2.36%
Non-nops are helped.

total systall in shared programs: 288317 -> 292975 (1.62%)
systall in affected programs: 87876 -> 92534 (5.30%)
helped: 388
HURT: 431
helped stats (abs) min: 1 max: 214 x̄: 14.39 x̃: 8
helped stats (rel) min: 0.25% max: 100.00% x̄: 22.12% x̃: 11.96%
HURT stats (abs)   min: 1 max: 232 x̄: 23.77 x̃: 7
HURT stats (rel)   min: 0.00% max: 1300.00% x̄: 51.71% x̃: 17.30%
95% mean confidence interval for systall value: 3.07 8.30
95% mean confidence interval for systall %-change: 9.49% 23.97%
Systall are HURT.

(The systall hurt is probably just due to having having fewer
instructions to hide latency with.)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14554>
 2022-01-18 17:44:50 +00:00
Mike Blumenkrantz
29cb1c7c13 zink: check EXT_image_drm_format_modifier for dmabuf support 
probably fixes https://gitlab.freedesktop.org/mesa/mesa/-/issues/5836

cc: mesa-stable

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14595>
 2022-01-18 17:12:50 +00:00
Juan A. Suarez Romero
68f16660f1 v3d: keep clear color untouched 
When invoking TLB clear, the color to clear could require
swapping and clamping.

Do the changes in a copy and leave the original color untouched, as it
is passed as constant.

This fixes local outside scope issues with Coverity.

Fixes: 54cba7d2 ("v3d: clamp clear color")
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14534>
 2022-01-18 15:22:07 +00:00
Marek Olšák
afdfcdd542 radeonsi: determine MEM_ORDERED after generating a shader variant 
because si_get_nir_shader runs NIR passes and some of them can introduce
new loads.

Fixes: 3fb77ef2e0 - radeonsi: do opt_large_constants & lower_indirect_derefs after uniform inlining

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14528>
 2022-01-18 11:11:08 +00:00
Marek Olšák
e5dd32a48c radeonsi: apply fbfetch/indirect_descriptor to uses_vmem_load_other earlier 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14528>
 2022-01-18 11:11:08 +00:00
Marek Olšák
08cc73a218 radeonsi: rename uses_vmem_* flags 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14528>
 2022-01-18 11:11:08 +00:00
Qiang Yu
ee040a6b63 radeonsi: enable ARB_sparse_texture2 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:11:53 +08:00
Qiang Yu
71a77aea79 radeonsi: enable multi sample sparse texture support 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
485ceb5c51 gallium: add multi_sample parameter to get_sparse_texture_virtual_page_size 
Instead of using actual sample count as parameter, we only use a bool
to indicate if the target is multi sample. This is because we don't
know the sample count when glGetInternalformativ() case.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
2c994e17c1 mesa/main: export _is_multisample_target for external usage 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
91661a3938 mesa/main: allow multi sample sparse texture 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
697e1cdeef radeonsi: lower nir_intrinsic_is_sparse_texels_resident 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
7d4b0b7789 glsl/nir: convert is_sparse_texels_resident to nir 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
634bb25123 glsl: add sparseTexelsResidentARB builtin function 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
a0b6515ec4 glsl/nir: adjust sparse texture nir_variable 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
3dc950118c glsl/nir: convert sparse image load to nir 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:36 +08:00
Qiang Yu
f4a972b748 glsl/nir: convert sparse ir_texture to nir 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
f62bbe44c9 glsl: add vec5 glsl types 
Used by nir_variable holds sparse texture output which is
up to vec5 size.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Singed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
59d94d8188 glsl: add sparse texture image load builtin functions 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
dcec15d79c glsl: add _texelFetch related sparse texture builtin function 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
a26dbfc24b glsl: add _textureCubeArrayShadow related sparse texture builtin func 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
640f909862 glsl: add _texture related sparse texture builtin functions 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
dd84769c55 glsl: ir_texture support sprase texture 
Sparse ir_texture will set is_sparse and use struct type to
hold both residency code and sampled texel.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
67b4c88512 glsl: add ARB_sparse_texture2 extension 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Singed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
d44f725ea6 mesa/main: relax alignment check when ARB_sparse_texture2 available 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
6da5136c66 mesa: add ARB_sparse_texture2 extension 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
fef018c307 gallium: add PIPE_CAP_QUERY_SPARSE_TEXTURE_RESIDENCY 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
5dd9cb1069 gallium/dd_debug: add get_sparse_texture_virtual_page_size 
Otherwise GALLIUM_DDEBUG=always crash when sparse texture is used.

Fixes: eed8421bba ("gallium: add screen get_sparse_texture_virtual_page_size callback")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Sigend-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Qiang Yu
2cee73f0f7 nir: fix nir_tex_instr hash not count is_sparse field 
This fixes nir_opt_cse miss replace a non-sparse tex instruction
with a sparse tex instruction and fail the nir_validate_shader().

Fixes: 3a7972f72a ("nir,spirv: add sparse texture fetches")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14362>
 2022-01-18 16:10:35 +08:00
Marek Olšák
3cafa3e852 ac/surface: allow displayable DCC with any resolution (e.g. 8K) 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14529>
 2022-01-18 01:44:17 -05:00
Danylo Piliaiev
e4c582ee71 tu: support VK_EXT_primitive_topology_list_restart 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14556>
 2022-01-17 15:21:03 +00:00
Rhys Perry
d95a0b52e4 nir/unsigned_upper_bound: don't follow 64-bit f2u32() 
Fixes Doom Eternal crash.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 72ac3f6026 ("nir: add nir_unsigned_upper_bound and nir_addition_might_overflow")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14555>
 2022-01-17 10:59:21 +00:00
Lucas Stach
0d65f229c5 egl/dri2: short-circuit dri2_make_current when possible 
If an application calls eglMakeCurrent with the same context and the same
draw and read surfaces as the current ones, there is no need to go
through all the work of unbinding/flushing the old context and binding
the new one.

While the EGL spec is a bit ambiguous here, it seems that the implicit
flush of the outgoing context only needs to be done when the context is
actually changed.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14379>
 2022-01-17 10:32:01 +00:00
Lucas Stach
b33ed5406a egl/dri2: remove superfluous flush when changing the context 
The flush of the outgoing GL context, as required by the EGL spec for
eglMakeCurrent and extended by KHR_context_flush_control, is already
performed in the unbindContext call. There is no need to pierce through
the layers and unconditionally call glFlush() here.

Getting the out-fence FD for explicit fencing needs to move behind the
unbindContext, to make sure we are getting the fence for the most
recently flushed commands.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14379>
 2022-01-17 10:32:01 +00:00
Samuel Pitoiset
88f1918919 radv/winsys: fix zero submit if no timeline semaphore support 
Kernels that don't support timeline semaphores also don't support
transferring syncobjs. Use export/import instead.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5845
Fixes: 967fc415fc ("radv: Add new submission path for use by the common sync framework.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14538>
 2022-01-17 08:38:29 +01:00
Emma Anholt
f6ffefba3e nir: Apply nir_opt_offsets to nir_intrinsic_load_uniform as well. 
Doing this for ir3 required adding a struct for limits of how much base to
fold in (which NTT wants as well for its case of shared vars), otherwise
the later work to lower to the 1<<9 word limit would emit more
instructions.

The shader-db results are that sometimes the reduction in NIR instruction
count results in the fewer sampler prefetches due to the shader being
estimated to be shorter (dota2, nexuiz):

total instructions in shared programs: 8996651 -> 8996776 (<.01%)
total cat5 in shared programs: 86561 -> 86577 (0.02%)

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14023>
 2022-01-16 19:11:29 +00:00
Emma Anholt
b024102d7c freedreno/ir3: Use nir_opt_offset for removing constant adds for shared vars. 
Saves some work in carchase and manhattan31:

instructions in affected programs: 2842 -> 2818 (-0.84%)
nops in affected programs: 1131 -> 1105 (-2.30%)
non-nops in affected programs: 1236 -> 1238 (0.16%)
mov in affected programs: 57 -> 61 (7.02%)
dwords in affected programs: 2144 -> 2150 (0.28%)
cat0 in affected programs: 1195 -> 1169 (-2.18%)
cat1 in affected programs: 151 -> 155 (2.65%)
cat2 in affected programs: 142 -> 140 (-1.41%)
sstall in affected programs: 190 -> 178 (-6.32%)
(ss) in affected programs: 63 -> 63 (0.00%)
systall in affected programs: 532 -> 511 (-3.95%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14023>
 2022-01-16 19:11:29 +00:00
Alyssa Rosenzweig
9645fa9107 agx: Handle discard intrinsics 
Lower to `sample_mask = 0`. Actually that implements a demote... doing
discard correctly probably requires rewriting the shader control flow to
insert a return where necessary...

Also, possibly we should be lowering this in NIR to play nice with
gl_SampleMask writes but that's a problem for when we understand the
hardware better.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14219>
 2022-01-16 18:23:28 +00:00
Alyssa Rosenzweig
f248f6623c agx: Add sample_mask instruction 
Sets the output sample mask to a given 8-bit immediate or 16-bit
register. Also used to implement discards, which is my ES2 interest.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14219>
 2022-01-16 18:23:28 +00:00
Alyssa Rosenzweig
dcc12656e3 asahi: Route sample mask from shader 
Compiler-controlled bit in the cmdstream.

Some other magic bits are needed for sample mask writes to work
properly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14219>
 2022-01-16 18:23:28 +00:00