Commit graph

172340 commits

Author SHA1 Message Date
Alyssa Rosenzweig
73bbf43bc0 agx: Plumb in nir_intrinsic_load_sample_mask_in
We have a special register for this, although this will need some lowering for
glSampleMask.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:49 +00:00
Alyssa Rosenzweig
6fd16dd7c9 agx: Model both sources of sample_mask
We need to control both sources to implement multisampling properly. The
semantic is something like:

   foreach sample in the first mask {
      if correspond bit in second bit set {
         make sample live
      } else {
         make sample dead
      }
   }

But I'm reticent to document more formally until the details are really
understood and properly tested.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:49 +00:00
Alyssa Rosenzweig
954e2eee29 asahi: Plumb ppp_multisamplectl into shaders
This lets us implement gl_SamplePositions in a cheap way with some ALU in the
shader preamble.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:49 +00:00
Alyssa Rosenzweig
17a05884b4 asahi: Plumb API sample mask into shaders
So we can lower glSampleMask() appropriately.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:49 +00:00
Alyssa Rosenzweig
bffbe099df asahi: Set uses_sample_shading for background program
If we read gl_SampleID we need the lowering, even though we don't call into
gather_info to set the bit for us. So set the bit manually.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:49 +00:00
Alyssa Rosenzweig
0b95d81150 agx: Assert that sample shading is lowered
Lest someone mess this up later and then try to "implement" these intrinsics in
the backend.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:48 +00:00
Alyssa Rosenzweig
46a5a99d24 asahi: Add alpha-to-coverage (and alpha-to-one) lowering
This should probably be shared code but meh.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:48 +00:00
Alyssa Rosenzweig
51e868f3a2 asahi: Add passes to lower sample intrinsics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:48 +00:00
Alyssa Rosenzweig
f28962e29a asahi: Add passes to lower MSAA
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:48 +00:00
Alyssa Rosenzweig
70b8babe3c agx: Use textures_used, not num_textures
The latter doesn't account for holes. Fixes regression in Neverball on Asahi.

Fixes: e607a89f ("mesa/main: ff-fragshader to nir")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:48 +00:00
Alyssa Rosenzweig
f1c2ea99e2 agx: Constant fold when optimizing int64
Otherwise we can get bcsel(false, ...) in the final optimized code, which isn't
great.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:48 +00:00
Alyssa Rosenzweig
9641fba9ba agx: Set support_16bit_alu
Allows some more optimizations.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
2023-06-07 03:21:48 +00:00
Gert Wollny
8068264469 r600/sfn: Switch to scoped barriers
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23272>
2023-06-07 02:37:22 +00:00
Gert Wollny
a12072868d r600/sfn: assert that group barrier is not emitted in divergent code flow
Also rename emit_barrier to emit_group_barrier

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23272>
2023-06-07 02:37:22 +00:00
Caio Oliveira
d0b7cf192b spirv: Add workaround for OpImageQueryLevels with Multi-sampled images
Warn and replace the query with the constant value 1.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9148
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23407>
2023-06-07 02:06:55 +00:00
Yonggang Luo
568209f57d compiler: Remove redundant struct glsl_type in nir_types.h
The struct glsl_type already declared in glsl_types.h

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23420>
2023-06-07 00:33:33 +00:00
Yonggang Luo
9e8135e936 compiler: Remove the need include "util/glheader.h" and "util/ralloc.h" in glsl_types.h
These includes can be moved into .cpp files and down-stream headers

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23420>
2023-06-07 00:33:33 +00:00
Yonggang Luo
1b836a52ea mesa, compiler: Move gl_texture_index to glsl_types.h
This move is done for decouple glsl_types.h from src/mesa/*

This is achieved by move gl_texture_index from src/mesa/main/menums.h to src/compiler/shader_enums.h
And move ATOMIC_COUNTER_SIZE,MAX_VERTEX_STREAMS from src/mesa/main/config.h to src/compiler/shader_enums.h

Move include main/[config|menums].h into glsl/glsl_parser_extras.h from glsl_types.h
As now glsl_types.h should not include headers from src/mesa/*

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23420>
2023-06-07 00:33:33 +00:00
Yonggang Luo
ab73f717d9 compiler: Move can_implicitly_convert_to helper to glsl module from glsl_types.h
This move is done for decouple glsl_types from glsl_parser_extras

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23420>
2023-06-07 00:33:33 +00:00
Yonggang Luo
f9860a84b3 compiler: Combine duplicated implementation of is_gl_identifier into glsl_types.h
As glsl_types.cpp also called is_gl_identifier, so move it into glsl_types.h,
this will help the decouple glsl_types.h from src/compiler/glsl/*

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23420>
2023-06-07 00:33:33 +00:00
Patrick Lerda
340311dac9 r600: fix r600_draw_vbo() buffer overflow
The previous implementation was copying the data using the
aligned length (size_dw). The aligned length could overflow
the original buffer size.

For instance, this issue is triggered with "piglit/bin/draw-batch -auto -fbo":
==5736==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fff139c77e8 at pc 0x7f25b350a9a0 bp 0x7fff139c6cb0 sp 0x7fff139c6460
READ of size 8 at 0x7fff139c77e8 thread T0
    #0 0x7f25b350a99f in __interceptor_memcpy (/usr/lib64/libasan.so.6+0x3c99f)
    #1 0x7f25a8fcdf24 in radeon_emit_array ../src/gallium/include/winsys/radeon_winsys.h:760
    #2 0x7f25a8fcdf24 in r600_draw_vbo ../src/gallium/drivers/r600/r600_state_common.c:2448
    #3 0x7f25a8ae7ba1 in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1791
    #4 0x7f25a7bc18ca in _mesa_validated_drawrangeelements ../src/mesa/main/draw.c:1696
    #5 0x7f25a7bc7e53 in _mesa_DrawElements ../src/mesa/main/draw.c:1824

Fixes: 0cf5d1f226 ("gallium: remove PIPE_CAP_INFO_START_WITH_USER_INDICES and fix all drivers")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23436>
2023-06-06 23:16:05 +00:00
Vinson Lee
ed759ad795 dzn: Fix qpool->queries_lock double lock
Fix defect reported by Coverity Scan.

Double lock (LOCK)
double_lock: mtx_lock locks qpool->queries_lock while it is locked.

Fixes: a012b21964 ("microsoft: Initial vulkan-on-12 driver")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23455>
2023-06-06 22:23:32 +00:00
Caio Oliveira
60664285a9 nir/print: Do not print raw values
In many cases the raw value is not really helpful,
since we only work with enums and the raw value is
already printed for indices without special printing.

If an index benefits from having special printing AND the
raw value, we can include the printing of the raw value
as part of its handler.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23375>
2023-06-06 21:50:34 +00:00
Mykhailo Skorokhodov
49c7fd7a7e iris: Fix memory size with disabled resizable bar
When the resizable bar feature is disabled,
then vram.mappable.size is only 256MB.
The second half of the total size is in the vram.unmappable.size variable.

Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23402>
2023-06-06 20:58:00 +00:00
Eric Engestrom
07207d12b0 ci/zink+radv: update expectations
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23465>
2023-06-06 20:24:25 +00:00
Eric Engestrom
9316ab74ef ci/radv: update expectations
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23465>
2023-06-06 20:24:24 +00:00
Alyssa Rosenzweig
99a00e2247 treewide: Use nir_trim_vector more
Via Coccinelle patches

    @@
    expression a, b, c;
    @@

    -nir_channels(b, a, (1 << c) - 1)
    +nir_trim_vector(b, a, c)

    @@
    expression a, b, c;
    @@

    -nir_channels(b, a, BITFIELD_MASK(c))
    +nir_trim_vector(b, a, c)

    @@
    expression a, b;
    @@

    -nir_channels(b, a, 3)
    +nir_trim_vector(b, a, 2)

    @@
    expression a, b;
    @@

    -nir_channels(b, a, 7)
    +nir_trim_vector(b, a, 3)

Plus a fixup for pointless trimming an immediate in RADV and radeonsi.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23352>
2023-06-06 18:52:25 +00:00
Alyssa Rosenzweig
68eda9456f treewide: Use nir_tex_src_for_ssa
Via Coccinelle patch:

    @@
    expression a, b, c;
    @@

    -a.src = nir_src_for_ssa(b);
    -a.src_type = c;
    +a = nir_tex_src_for_ssa(c, b);

    @@
    expression a, b, c;
    @@

    -a.src_type = c;
    -a.src = nir_src_for_ssa(b);
    +a = nir_tex_src_for_ssa(c, b);

Plus manual fixups, including...

* a few identity swizzles changed to nir_trim_vector in TTN and prog-to-nir to
  fix the Coccinelle-botched formatting, and similarly a pointless nir_channels
* collapsing a now-pointless temp in vtn

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23352>
2023-06-06 18:52:25 +00:00
Alyssa Rosenzweig
3863280399 nir: Add and use nir_tex_src_ssa
This makes texture instructions a lot less annoying to construct, especially in
cases where the deref-based helpers don't work.

I only converted core NIR, not the drivers. Since it was by hand.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23352>
2023-06-06 18:52:24 +00:00
Marek Olšák
218c00319b amd: remove unused PKT0 definitions
We never use type 0 packets.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:36 +00:00
Marek Olšák
dd5604b94d radeonsi: don't use SET_SH_REG_INDEX if the kernel doesn't use CU reservation
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:36 +00:00
Marek Olšák
d98501f5c1 radeonsi: don't use SET_SH_REG_INDEX on gfx7-9
It was accidentally used with geometry shaders. It might have caused hangs.

Fixes: ccaaf8fe04 - amd: massively simplify how info->spi_cu_en is applied

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:36 +00:00
Marek Olšák
0fecee53cf radeonsi: re-indent gfx10_create_sh_query_result_cs
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:36 +00:00
Marek Olšák
acde68b282 radeonsi/ci: add gfx6 failures
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:36 +00:00
Marek Olšák
c2b655d788 radeonsi: add a separate cdna_init_compute_preamble_state function
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:36 +00:00
Marek Olšák
7baeb54c2a radeonsi: don't set registers set by CLEAR_STATE in the preamble for gfx10-11
CLEAR_STATE doesn't clear PA_SC_GENERIC_SCISSOR_* only on some older chips

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:36 +00:00
Marek Olšák
5acff16ce4 radeonsi: add a separate gfx10_init_gfx_preamble_state function
and set the registers in an order sorted by the offset.

It's less of a mess now.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
c4d465a514 radeonsi: add helpers to create and clone a sized pm4 state
to simplify si_init_cs_preamble_state and it will be used in the following
commits

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
c23597970b radeonsi: don't program COMPUTE_MAX_WAVE_ID (GDS register) on gfx6
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
ead53b62c9 radeonsi: optimize no-op primitive restart index changes thanks to index masking
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
ade70712df radeonsi: rename the msaa_sample_locs state to sample locations
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
d0e141ca73 radeonsi: merge si_emit_msaa_sample_locs with si_emit_sample_locations
Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
b8fef52f0c radeonsi: move PA_SU_SMALL_PRIM_FILTER_CNTL to the preamble when possible
PA_SU_SMALL_PRIM_FILTER_CNTL is set in the gfx preamble if the sample loc
bug isn't present. Else, it's set as part of sample locs state.

This is part 3 of simplifying si_emit_msaa_sample_locs.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
547fccaab9 radeonsi: adjust 16x EQAA sample locs to make PA_SU_PRIM_FILTER_CNTL immutable
and move PA_SU_PRIM_FILTER_CNTL to the gfx preamble.

If sample locations don't use the -8 coordinate, the EXCLUSION can always
be set to 1.

This is part 2 of simplifying si_emit_msaa_sample_locs.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
818381dfbd radeonsi: always set sample locations even for 1x MSAA for simplicity
This is part 1 of simplifying si_emit_msaa_sample_locs.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
f6d861a1c1 radeonsi: move PA_CL_NGG_CNTL emission into rasterizer state
It's a better place. Edge flags only have effect if polygon mode is
enabled. Changing shaders should no longer roll the context due to line
culling flipping EDGE_FLAG_ENA.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
941e214fe7 radeonsi: reorder and comment tracked registers
Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
d7802b02c4 radeonsi: split tracked_regs masks into context registers and other registers
Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
9cf2e47833 radeonsi: increase SDMA gfx9+ limits
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00
Marek Olšák
52f94e2b93 radeonsi: decompress DCC for SDMA if we're really going to use SDMA
change the order of operations

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-06 18:01:35 +00:00