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radeonsi: move PA_CL_NGG_CNTL emission into rasterizer state

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It's a better place. Edge flags only have effect if polygon mode is
enabled. Changing shaders should no longer roll the context due to line
culling flipping EDGE_FLAG_ENA.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
This commit is contained in:
Marek Olšák 2023-05-14 19:52:47 -04:00 • committed by Marge Bot
parent 941e214fe7
commit f6d861a1c1
5 changed files with 7 additions and 14 deletions
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1
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -273,7 +273,6 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_TF_PARAM] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x3;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_NGG_CNTL] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL] = 0;

1
src/gallium/drivers/radeonsi/si_shader.h
View file

@ -949,7 +949,6 @@ struct si_shader {
unsigned spi_shader_idx_format;
unsigned spi_shader_pos_format;
unsigned pa_cl_vte_cntl;
unsigned pa_cl_ngg_cntl;
unsigned vgt_gs_max_vert_out; /* for API GS */
unsigned ge_pc_alloc; /* uconfig register */
unsigned spi_shader_pgm_rsrc3_gs;

7
src/gallium/drivers/radeonsi/si_state.c
View file

@ -1073,6 +1073,13 @@ static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rast
polygon_mode_enabled ||
rs->perpendicular_end_caps : 0));
if (sscreen->info.gfx_level >= GFX10) {
si_pm4_set_reg(pm4, R_028838_PA_CL_NGG_CNTL,
S_028838_INDEX_BUF_EDGE_FLAG_ENA(rs->polygon_mode_is_points ||
rs->polygon_mode_is_lines) |
S_028838_VERTEX_REUSE_DEPTH(sscreen->info.gfx_level >= GFX10_3 ? 30 : 0));
}
if (state->bottom_edge_rule) {
/* OpenGL windows should set this. */
si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,

1
src/gallium/drivers/radeonsi/si_state.h
View file

@ -280,7 +280,6 @@ enum si_tracked_context_reg
SI_TRACKED_VGT_TF_PARAM,
SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL, /* GFX8+ */
SI_TRACKED_PA_SC_BINNER_CNTL_0, /* GFX9+ */
SI_TRACKED_PA_CL_NGG_CNTL, /* GFX10+ */
SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, /* GFX10+ */
SI_TRACKED_GE_NGG_SUBGRP_CNTL, /* GFX10+ */
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, /* GFX10.3+ */

11
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -1186,9 +1186,6 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader
shader->ngg.spi_shader_pos_format);
radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
shader->ngg.pa_cl_vte_cntl);
radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
shader->ngg.pa_cl_ngg_cntl);
radeon_end_update_context_roll(sctx);
/* These don't cause a context roll. */
@ -1397,14 +1394,6 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
S_028B90_ENABLE(gs_num_invocations > 1) |
S_028B90_CNT(gs_num_invocations) |
S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance);
/* Output hw-generated edge flags if needed and pass them via the prim
* export to prevent drawing lines on internal edges of decomposed
* primitives (such as quads) with polygon mode = lines.
*/
shader->ngg.pa_cl_ngg_cntl =
S_028838_INDEX_BUF_EDGE_FLAG_ENA(gfx10_edgeflags_have_effect(shader)) |
S_028838_VERTEX_REUSE_DEPTH(sscreen->info.gfx_level >= GFX10_3 ? 30 : 0);
shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, true);
if (gs_stage == MESA_SHADER_GEOMETRY) {