This speeds up glReadPixels. Instead of reading from the write-combined
framebuffer and converting colours on the CPU, this blits on the GPU to a
writeback staging resource with the colour conversion for free, and memcpies
from the writeback staging resource on the CPU.
In general, due to textures being write combined and tiled/compressed by default
by staging resources being linear writeback, blit-based texture transfer should
win out (you were going to blit anyway), particularly when format conversion is
involved
33% reduction in wall clock time for grim at 4K. No change in deqp-gles2
runtime.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>
When playing the My Little Pony theme song at 1080p on T8103, with mpv's GPU
compositing but software decoding, CPU usage drops from 200% to 50% due to
proper caching of the staging resource.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>
We only need 4 byte alignment, not 8 bytes. This isn't a big difference in
practice, but it probably reduces padding in some cases. More importantly, it
corrects our XML to match what the hardware actually does, which is great.
(There is exactly enough room for a 40-bit address with 4 byte alignment.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>
There's a corner case where 3D textures have extra padding compared to 2D
arrays. We need to communicate that to ail.
Fixes
dEQP-GLES3.functional.texture.specification.texstorage3d.size.3d_32x16x64_4_levels.
That test now uses the same layout as Metal.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>
Builds on the work of !15121. This gets to delete even more code
because many drivers shared a lot of code for i2b and f2b.
No shader-db or fossil-db changes on any Intel platform.
v2: Rebase on 1a35acd8d9.
v3: Update a comment in nir_opcodes_c.py. Suggested by Konstantin.
v4: Another rebase. Remove f2b stuff from Midgard.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20509>
There were only two users. Replace each with nir_fneu instead.
This is now a squash of what was two separate commits.
nir_lower_pstipple_block is called after nir_lower_bool_to_int32, so
nir_fneu32 has to be used here or there will be regresssions in stipple
tests on llvmpipe.
v2: Rebase on !20869.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20509>
it's annoying to validate this at runtime since it has to happen during draw,
but storing the "usable" ds3 mode separately from the pipeline state should
be a reasonable enough compromise for perf here...hopefully
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>
apparently an actual null descriptor is illegal here, and it's wasted cpu
anyway, so just cache the dummy surface on init and use that data when
fbfetch isn't active but the layout requires it
Fixes: 7ab5c5d36d ("zink: use EXT_descriptor_buffer with ZINK_DESCRIPTORS=db")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>
Instead of generating num_components*simdwidth scattered stores, if
there's no indirect then we can just look up the pointer to the
base_offset and do a simd store there.
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i64vec4 goes
from 30s to ~2s.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>
This now matches how they get dereffed by get_soa_array_offsets() -- each
array element has num_components vecs inside of it, rather than each
components has an array in it.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>
This should be way faster to compile by not spamming so many loops at
LLVM, and faster to execute if LLVM didn't figure out what that loop
meant.
It looks vector reduce ops aren't really a thing, just a convenience in
the IR. We should be able to do better by counting zeroes in the
exec_mask != 0 result.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
46 -> 30 seconds on
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i16vec4 by
not spamming LLVM with so many loops.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
Dynamic texture indices had a similar "find an active channel" loop,
though it happened to use the last active channel rather than the first.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
We don't need to deref invoc inside -- invoc is uniform in active
channels, so we can find our first active invocation in the loop, and then
dereference invocation once outside.
50 -> 46 seconds on
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i16vec4
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
This uses the new pass to lower tex coordinates late, which gets us one step
closer to preprocessing NIR at CSO create time instead of variant create time.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>
This pass needs to run early (because it depends on early I/O), but it doesn't
actually need the shader key. Why not? If we overestimate the number of render
targets, extra store_output intrinsics will be generated, but they will be
deleted by AGX tilebuffer lowering later.
Note we'll probably want something smarter than this for fragment epilogues in
the future to avoid piles of unnecessary moves.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>
Support for FDO etag http header.
Includes line-smooth-stipple test improvements.
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20875>
We have moved si_nir_assign_param_offsets before output lowering
pass, so there won't be primitive id store output when VS/TES here.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
We may remove some outputs when si_nir_kill_outputs and
ac_nir_optimize_outputs, so update the outputs written
info for output lower pass to skip manipulating these
outputs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
gs copy shader is going to emit nir_export_amd directly so this vertex
color clamp pass which apply to nir_store_output will not work.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Because the place that called util_iround are always ensured
that INT_MIN <= f <= INT_MAX
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19978>
