The firmware reports no MALL cache being present, which is wrong. We
later depend on correct L3 cache size values for choosing the attribute
ring size, so fall back to manually computing the size.
Fixes: 355242f055 ("ac/gpu_info: adjust attribute ring size for gfx11")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26147>
This marks them as Unified in the RGP UI and shows the compute shader
view.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26158>
ApiRayTracingSeparateCompiled can only used by trace commands.
Fixes: bfb55d0 ("ac/sqtt,radv/sqtt: Add and use marker for separate RT compilation")
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26158>
This version of the lua wrap fixes installation of the library which
was previously causing liblua SOs to be missing when Mesa was installed
using `meson install`.
Signed-off-by: Mark Collins <pixelyion@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26185>
Both null def and op result in the same correct encoding, but these
instructions optionally read a sgpr, so it makes more sense to use an operand.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26163>
When lowering @load_constant to @load_ubo, the bit size is currently
hard-coded to 32. This causes validation errors when lowering a constant
with a 64b bit size.
This patch fixes this by setting the @load_ubo bit size correctly for
64b constants. This 64b load is later lowered to a 32b load by
ir3_nir_lower_64b_intrinsics.
Fixes Piglit test:
- spec@arb_gpu_shader_fp64@execution@fs-indirect-temp-double-src
This patch has no impact on shader-db.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26191>
Nobody has to advertize it as an extension, but here we are.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25701>
There is no real reason to prevent this as far as I know. And some of the
SPIR-V generated by DPCPP is running into this.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25701>
Shader Local Memory is what NVIDIA calls it in the shader header docs as
well as the command stream headers. Better to be consistent even if it
gets my Intel brain confused. (Intel uses SLM for shared memory.)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26197>
At this point, we're fully trusting NAK to do its own lowering and we
only lower stuff in nvk_shader.c if it's relevant for Vulkan. This also
assumes that NAK is already doing the right thing everywhere.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26197>
This reverts commit 578e10e157.
The only reason for reallocating surfaces as interlaced (on drivers
that supports both progressive and interlaced) was deinterlacing
with postproc filter, but that now also supports interleaved surfaces.
With this change interlaced surfaces are no longer used on radeonsi.
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26174>
The code here handled stores of actual 3-byte values (8-bit, 3-component), but didn't
correctly handle stores of larger 8-bit vectors that were constrained by write mask to
just 3 bytes. In that case, the pad-to-vec4 step was unnecessary and problematic.
Seen in CL CTS test_basic vector_swizzle test group for char3 with CLOn12.
Fixes: c70d94a8 ("nir_lower_mem_access_bit_sizes: Support unaligned stores via a pair of atomics")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26034>
This gives FS I/O the same treatment as we did for vertex attributes in
that we now have a NIR intrinsic which pretty closely matches the
hardware and we lower to that before going into NAK. This gives us a
bit more control in the NIR.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26181>
