Commit graph

188004 commits

Author SHA1 Message Date
Job Noorman
434b82469f ir3: make const_imm_index_to_reg helper public
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
2025-03-06 08:47:54 +00:00
Job Noorman
68ab25e6d4 ir3: split immediate state from rest of const state
On a7xx, the immediates that get promoted to const registers will be
initialized in the preamble instead of being part of the const state. So
technically, we won't need the immediate state that is part of the const
state anymore on a7xx. However, it is still a convenient place for
ir3_cp to store the immediates that should be promoted to const
registers before they are lowered to the preamble.

This causes one issue: the binning pass isn't allowed to modify the
const state while it's perfectly fine for it to use different immediates
compared to the non-binning pass on a7xx. Even pre-a7xx this is fine as
long as the size of the immediate buffer is the same.

To allow the binning pass to modify its immediate state while keeping
its const state immutable, this commit moves the fields related to
immediates into a new struct. Runtime checks are added to enforce that
the size of the immediate buffer is the same for the binning and
non-binning variant pre-a7xx.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
2025-03-06 08:47:54 +00:00
Job Noorman
f9fc0fc8fd ir3/sched: handle dependencies between stc and const reads
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
2025-03-06 08:47:54 +00:00
Job Noorman
0f6ec14925 ir3: fix false dependencies of rpt instructions
When merging multiple instructions into one rpt instruction, the false
deps of the rpt instruction should be the union of the false deps of its
parts.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 4c4366179b ("ir3: add post-RA pass to merge repeat groups into rptN instructions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
2025-03-06 08:47:54 +00:00
Job Noorman
62d2069617 ir3: add helper to create STC
Creating STC is complicated since we might need to use a1.x for
addressing. Extract the current code into a helper so that it can be
used elsewhere.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
2025-03-06 08:47:53 +00:00
Job Noorman
3186443057 ir3: remove hash table for a1.x
Removing duplicates is now supported by ir3_cse so the hash table is
unnecessary. Removing it will make it easier to create instructions
using a1.x without having access to ir3_context.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
2025-03-06 08:47:53 +00:00
Job Noorman
06978e0c0c ir3/cse: add support for mov a0.x/a1.x
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
2025-03-06 08:47:53 +00:00
Job Noorman
ac18eccd74 ir3: add ir3_cursor_current_block helper
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
2025-03-06 08:47:53 +00:00
Lorenzo Rossi
69982e6f2f nak: Flatten AttrAccess into instructions
The AttrAccess structure provided inputs for similar instructions, some
inputs were used only in a subset of instructions, needing asserts and
dummy values.
This commit flattens the struct directly in the instructions removing
the unused fields and cleaning up the code.

Signed-off-by: Lorenzo Rossi <snowycoder@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33899>
2025-03-06 05:29:56 +00:00
Corentin Noël
24dbc278f0 tnn: nir: Don't use deprecated NIR_PASS_V macro anymore
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686>
2025-03-06 03:29:21 +00:00
Corentin Noël
acd5f2971a ntt: nir: Don't use deprecated NIR_PASS_V macro anymore
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686>
2025-03-06 03:29:20 +00:00
Corentin Noël
eb1274ef08 nir: Add bool return value to nir_legacy_trivialize(..)
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686>
2025-03-06 03:29:20 +00:00
Corentin Noël
8eae89f3f0 virgl: nir: Don't use deprecated NIR_PASS_V macro anymore
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686>
2025-03-06 03:29:20 +00:00
Christian Gmeiner
71e2ddcede etnaviv/ci: Add gles2 run for GC3000
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33838>
2025-03-06 03:09:12 +00:00
Assadian, Navid
9a88afecbd amd/vpelib: More parameters to the segmentation process and introduce validation hook
Generalization for the following:
1. pass in the scaler output alignment requirement to segment number determination function
2. parameter validation hook

Signed-off-by: Navid Assadian <Navid.Assadian@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
2025-03-06 02:11:53 +00:00
Zhao, Jiali
37c244998a amd/vpelib: Fix studio output CSC
Fix studio output CSC.

Signed-off-by: Jiali Zhao <Jiali.Zhao@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Evan Damphousse <Evan.Damphousse@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
2025-03-06 02:11:53 +00:00
Visan, Tiberiu
da04cbca66 amd/vpelib: Apply normalization for full range
[WHY]
The full range needs to have the same brightness normalization like the
studio range.

[HOW]
Apply the same normalization.

Signed-off-by: Tiberiu Visan <Tiberiu.Visan@amd.com>
Reviewed-by: Tomson Chang <Tomson.Chang@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
2025-03-06 02:11:53 +00:00
Visan, Tiberiu
b3d43cea08 amd/vpelib: Fix studio range
[WHY]
Studio signal has an offset.

[HOW]
Subtract that offset.

Signed-off-by: Tiberiu Visan <Tiberiu.Visan@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
2025-03-06 02:11:53 +00:00
Leder, Brendan Steve
69c331e2c0 amd/vpelib: Reformat index variables and update enum
Reformat index variables to indicate loop specifics and update enum to match formatting guide.

Signed-off-by: Brendan Steve Leder <Brendansteve.Leder@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Evan Damphousse <Evan.Damphousse@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
2025-03-06 02:11:53 +00:00
Vasily Khoruzhick
6528ee4228 lima: ppir: reuse load_temp/store_temp nodes if possible
Currently spilling code operates on individual ops rather than on
instructions, and as a result it may create a redundant load_temp op if
an instruction references spilling register several times.

Similarly, it creates multiple stores if there are multiple ops in the
instruction that write different components of the register.

Check whether the instruction already contains a necessary load_temp or
store_temp and reuse it if possible.

shader-db:

total instructions in shared programs: 27718 -> 27673 (-0.16%)
instructions in affected programs: 2786 -> 2741 (-1.62%)
helped: 18
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 2.50 x̃: 1
helped stats (rel) min: 0.39% max: 5.33% x̄: 2.05% x̃: 0.80%
95% mean confidence interval for instructions value: -3.70 -1.30
95% mean confidence interval for instructions %-change: -3.09% -1.01%
Instructions are helped.

total loops in shared programs: 4 -> 4 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 390 -> 381 (-2.31%)
spills in affected programs: 145 -> 136 (-6.21%)
helped: 9
HURT: 0

total fills in shared programs: 1210 -> 1174 (-2.98%)
fills in affected programs: 149 -> 113 (-24.16%)
helped: 9
HURT: 0

LOST:   0
GAINED: 0

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33753>
2025-03-06 01:48:55 +00:00
Mike Blumenkrantz
7200cf8827 radv: don't unnecessarily flag prolog recalc when binding VBOs
another 25% for vkoverhead@draw_vbo_change_dynamic

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
4f71370830 radv: get vbo info directly into dgc upload
don't need this memcpy

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
b78835de13 radv: move non_trivial_format calc to dynamic VI bind
this otherwise gets pointlessly recalculated on every draw when a VBO changes

another 10% for vkoverhead@draw_vbo_change_dynamic

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
42db08c275 radv: split out dynamic vertex input descriptor writing
~25% boost to vkoverhead@draw_vbo_change_dynamic

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
22434edefc radv: inline some vertex descriptor functions
+5-7% in vkoverhead 16

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
00f51f7215 radv: eliminate a memset in radv_get_vbo_info()
very minor perf cost

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
e2ccd638a8 radv: roll line topology dynamic state changes into existing rast samples flag
this eliminates uploading rast samples whenever prim type changes even
when rast samples will not be changed

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
b2123314bd radv: store vertex prolog simple input check to cmdbuf on vs bind
no need to check this again and again

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
881d94a40a radv: store num_attributes to shader info
this eliminates a util_last_bit from the prolog hotpath

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Mike Blumenkrantz
d40dd4bfb7 radv: rewrite radv_get_line_mode() conditional
this was weirdly hard to parse

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806>
2025-03-06 01:26:02 +00:00
Alyssa Rosenzweig
6c24ac7d21 panfrost: clean up CL meson rules
we shouldn't need any of this anymore. I cleared out similar gunk from Asahi, we do the same for Panfrost here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
2025-03-06 00:43:59 +00:00
Alyssa Rosenzweig
4d6e37066a meson,clc: set CL standard from meson
this is slightly less weird I think.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
2025-03-06 00:43:59 +00:00
Alyssa Rosenzweig
c0022b6603 intel: use common CL args
this contains two behaviour changes:

* NDEBUG no longer set in debug builds (so asserts work in debug, but are still
  stripped out in release as expected).
* macro map set properly for assertions to be reported with proper paths.

together this makes assertions do the right thing on Intel and brings us in
alignment with asahi+panfrost

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
2025-03-06 00:43:59 +00:00
Alyssa Rosenzweig
f35172b6a4 meson: make CL args common
this will let us unify behaviour across drivers a bit more.

no functional change here. (intel is specifically excluded to avoid a functional
change.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
2025-03-06 00:43:59 +00:00
Caio Oliveira
54912281a0 brw: Always verify EU compaction in debug mode
There's already code to verify that any compacted instruction
that we produce is equivalent to the original uncompacted
instruction -- including detailed output if it fails.

This patch enables this verification in debug build and will
abort in case it fails.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33821>
2025-03-06 00:14:14 +00:00
Caterina Shablia
a9592a0c15 panvk: enable subgroupExtendedTypes
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365>
2025-03-05 22:58:15 +00:00
Caterina Shablia
c4941376a9 pan/bi: lower subgroups before lowering int64
nir_lower_int64 doesn't know how to lower 64-bit imul reductions and
scans. Lowering subgroup operations first leaves us with just 64-bit
ballot and read_invocation, which are easily lowered.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365>
2025-03-05 22:58:15 +00:00
Caterina Shablia
0f520e3d5a pan/bi: lower non-32-bit ballot{,_relaxed}
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365>
2025-03-05 22:58:15 +00:00
Caterina Shablia
14cecd0621 pan/bi: ensure src bit sizes of ballot{,_relaxed} and read_invocation
* ballot{,_relaxed}'s src[0] must always be a 32-bit value.

 * read_invocation's src[0] must always be at most 32-bit value. While
   the HW instruction always operates on a 32-bit value, it's important
   to remember that it's just a data movement operation, so garbage in
   the high bits of a 32-bit value representing a narrower value don't
   present an issue.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365>
2025-03-05 22:58:15 +00:00
Caterina Shablia
ca9ff8c8c7 nir: teach nir_lower_bit_size to handle ballot and ballot_relaxed
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365>
2025-03-05 22:58:15 +00:00
Alyssa Rosenzweig
386e777cad v3dv: fix clang warning
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33878>
2025-03-05 21:28:53 +00:00
Alyssa Rosenzweig
8b7389b1a9 asahi: port to common stats framework
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33814>
2025-03-05 20:50:17 +00:00
Alyssa Rosenzweig
722b83434a util: add shader statistic framework
All mature drivers report shader statistics in various places. GL drivers use
util_debug for shader-db's report script. VK drivers use executable statistics
feeding the report fossil script. Many drivers also have a magic env var to
dump the stats to stdout/stderr in addition to these standard forms.
Implementing any of these 3 reports requires doing brittle string processing in
C (GL, stdout) or piles of boilerplate (VK). Additionally, the logic gets
duplicated in every driver and duplicated between GL and VK.

And to add insult to injury, the information is duplicated *again* in the report
fossil script :'(

This commit introduces a new 'shader statistic framework' that aims to unify
statistics reporting across all drivers and across GL&VK. With the new approach,
a common XML file defines all the statistics for the tree. The common code
introduced here then autogenerates from that XML file an appropriate C header.
The header contains a C struct for each ISA, and autogenerated print/report
functions. Minimal driver integration is required: just filling out the stats
struct and calling the appropriate functions.

In this MR, 3 driver families are added as examples. Panfrost/PanVK and
Asahi/Honeykrisp are added as "complete" examples. Neither Vulkan driver
reported nontrivial executable statistics; with these changes, both report all
the same statistics that the GL drivers report. Turnip is also added partially -
it's not plumbed into ir3/gallium yet but just using the XML reduces boilerplate
a ton for Vulkan statistics.

[It is intended for this XML to be consumed also by shader-db's python scripts,
but that's not done here.]

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33814>
2025-03-05 20:50:17 +00:00
Alyssa Rosenzweig
2a44266d57 vulkan: add helpers to work with executable statistics
this is a lot of boilerplate in each driver. add helpers for it instead. the
common framework will use these internally, but drivers that don't want the
framework for whatever reason could use these themselves too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33814>
2025-03-05 20:50:17 +00:00
Samuel Pitoiset
682723c0c4 spirv/tests: add a test for lower_terminate_to_discard
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33866>
2025-03-05 19:56:50 +00:00
Samuel Pitoiset
40ea8c2edc spirv/tests: add a test for force_tex_non_uniform
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33866>
2025-03-05 19:56:50 +00:00
Samuel Pitoiset
74e1cebd02 spirv/tests: add a test for force_ssbo_non_uniform
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33866>
2025-03-05 19:56:50 +00:00
Samuel Pitoiset
2e3e3249b8 spirv/tests: add a test for NonSemantic.DebugBreak
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33866>
2025-03-05 19:56:50 +00:00
Samuel Pitoiset
c9eb0a2db5 spirv/tests: initialize compiler options in constructor
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33866>
2025-03-05 19:56:50 +00:00
Samuel Pitoiset
f2eb31b1a2 spirv: move workarounds to an inner struct in spirv_to_nir_options
To be more explicit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33866>
2025-03-05 19:56:50 +00:00