pvr_cmd_buffer_end_sub_cmd() sets the current sub-command to NULL. This was
causing list_move_to(), which is called immediately after this, to access a NULL
pointer. Fix this by storing the current sub command before calling
pve_cmd_buffer_end_sub_cmd() so that this can be used instead when modifying the
list.
Fixes: d1b17a5edc ("pvr: Implement ZLS subtile alignment")
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
Waits were not previously being created for job dependencies in
pvr_driver_queue_submit() because the pvr_stage_mask() was being called in place
of pvr_stage_mask_dst(), and the former does not handle the top-of-pipe bit.
Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
This prevents the creation of unused syncobjs in the kernel by not processing
waits when there aren't any waits given in the submit info.
Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
The descriptor set code will undergo a rework fairly soon so instead of trying
to fixup `per_stage_descriptor_masks` and deal with possible side effects of
that, for now let's always regenerate all descriptor program data sections no
matter the stage mask.
Fixes the following:
dEQP-VK.pipeline.monolithic.dynamic_offset.graphics
.{multi,single_}set.{storage,uniform}_buffer.numcmdbuffers_1
.sameorder.numdescriptorsetbindings_2.numdynamicbindings_1
.numnondynamicbindings_0
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
In `pvr_create_renderpass_hwsetup()` we use the size of the pbe accum format to
setup a mask for the valid parts of the output regs.
For formats such as `E5B9G9R9_UFLOAT_PACK32` which aren't supported as colour
attachments, `vkCreateRenderPass()` can still be called so to avoid undefined
behavior we use `0` as the bitsize.
Fixes `Unknown pbe accum format. Implementation error` for:
dEQP-VK.api.granularity.in_render_pass.e5b9g9r9_ufloat_pack32
dEQP-VK.api.granularity.multi.e5b9g9r9_ufloat_pack32
dEQP-VK.api.granularity.random.e5b9g9r9_ufloat_pack32
dEQP-VK.api.granularity.random.r32g32b32_uint
dEQP-VK.api.granularity.random.r32g32b32a32_sint
dEQP-VK.api.granularity.single.e5b9g9r9_ufloat_pack32
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
The accumulation format must be used here, not the final PBE emitted format.
Signed-off-by: SoroushIMG <soroush.kashani@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
The TEXC(GRDESC) instruction returns the LOD for a given texture
coordinates. Use it to implement nir_texop_lod.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31742>
The TEX_GRADIENT instruction returns the LOD for a given texture
coordinates. Use it to implement nir_texop_lod.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31742>
Define the TEX_GRADIENT instruction in valhall/ISA.xml, and add the
necessary bits to the compiler to expose it.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31742>
These bits are reserved in the spec. Even if setting them is harmless,
we'd rather keep them zero just in case.
Suggested-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31742>
The LOD bias in encoded in a signed 8.8 fixed point, meaning the valid
range is [-128,+127.966] not [-255,+255]. Since .maxSamplerLodBias
encodes an absolute value not a range, we make it [-127.996,+127,996].
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31742>
In rare cases, it could happen that during post-RA validation,
live-var-analysis sets needs_vcc = false after if was true
before register allocation.
Fixes: bb5eace0dc ('aco/live_var_analysis: check for isPrecolored flag rather than isFixed')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31791>
This does shader analysis that is more niche than regular shader info.
It's planned to be used by nir_restructure_tcs_flow as discussed here:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/11910
It's also useful for driver-specific passes.
The code for gathering "all_invocations_define_tess_levels" is copied
from radeonsi. The rest is new.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31447>
Perfetto is allowed to choose it's own default clock, and before this we just assumed the presentation times reported by the compositor are the same as perfetto's internal clock, which is not always the case. I got a nasty trace where all the wayland presents were in the wrong location. This fixes that by asking the compositor which clock it uses, then passing that along to perfetto.
A workaround for my compositor was setting use_monotonic_clock=true in the perfetto config, as my compositor (and I suspect most others) use the monotonic clock for presentation timestamps. However, asking the compositor is definitely the most correct solution.
I added a clock param to `MESA_TRACE_TIMESTAMP_{BEGIN,END}`, as it's only use that I could see was in wsi_common_wayland, and in general it seems good to be careful about which clock tracing timestamps come from.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31779>
Fixes: 4aa3b2d ('anv: LNL+ doesn't need the special flush for sparse')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31737>
Emit dummy VF_STATISTICS state before each VF state.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31759>
Emit dummy VF_STATISTICS state before each VF state.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31759>
Running LTO on pre-merge can be time-consuming,
especially on (over)loaded CI.
Let's keep it in nightly jobs to ensure coverage without causing
timeouts in pre-merge pipelines.
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31790>
In function 'r600_init_resource_fields',
inlined from 'r600_buffer_create' at ../src/gallium/drivers/r600/r600_buffer_common.c:561:2:
../src/gallium/drivers/r600/r600_buffer_common.c:121:48: error: array subscript 'struct r600_texture[0]' is partly outside array bounds of 'unsigned char[256]' [-Werror=array-bounds=]
121 | if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
| ^~~~~~~~~~~~~~~~~~~~~~~~
In file included from ../src/util/os_memory.h:37
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31790>
This moves the generate-gfxstream-vulkan.sh script
to upstream Mesa too. Right now, Mesa is the source
of truth for both guest and host codegen.
There needs to be a simple way to invoke genvk.py
for users. The script assumes the AOSP directory
structure to find gfxstream host, but the user may
also pass the path to gfxstream as the first argument.
Please run this from the src/gfxstream/codegen directory.
Reviewed-by: Marcin Radomski <dextero@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31775>
Enable guest side support for external memory on host devices
with VK_EXT_external_memory_metal extension.
Keeping old moltenvk extension check for backwards compatibility.
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31775>
We used to only store Temps in the stack, so undef meant exec.
Then the stack was changed to operands, and some places started storing exec
directly, drop the undef handling by replacing everything with Operand(exec, lm)
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31560>
Iris also makes use of compute engine in paralel with render engine,
so here also programing the async compute registers like it is done
in ANV.
This should improve performance when render and compute engine
are running in parallel.
It was also necessary to copy 2 workarounds that are needed before
programing STATE_COMPUTE_MODE.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
This recommended values should improve the performance of async
compute in gfx20, we may want to tweek this for Linux but at least
this values should give us a better baseline than default values.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
Setting the missing registers to specification recommended values that
is also the default value, so it is not expected any changes in
behavior or performance here.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
DG2 has the 'Force Non-Coherent' fields but MTL and ARL has
'Z Async Throttle settings', so here adding the missing one.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
While this should not cause any real issues, there is no reason
to unlock the mutex just to lock it again couple lines below.
Fixes coverity issue 1559431 Value not atomically updated
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31622>
Bit shift would go over 32 bits. Also add assert for maximum
value as allowed by spec.
Fixes coverity issue 1469252 Bad bit shift operation
Fixes: 5edbecb856 ("frontends/va: adding va av1 encoding functions")
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31622>
